Re: Dreaming in Technicolor

Yevgeni Tunik wrote:
> Bob,
> 
> 1. For my guess, your dreaming isn't realistic for the following items.
> 
>> I/O Voltage:       3.3v. 5v tolerant
> Microcontroller with 5V IO is sure not low-power.
> 

5V tolerance is also not very compatible with a low-voltage process for 
a <= 1.8V core.

>> AtoD:              8 ch 12 bit, 100+ Ksps
> Any 12 bit ADC on the CPU silicon is unknown for me. I guess, the reason is
> the noise. Possibly, QSPI connected external ADC (e.g. Maxim) will be a good
> choise.
> 

There are plenty of microcontrollers with 12-bit ADC on board (many 
msp430's, for example, and there are a number of Analogue Device chips 
that are basically good ADCs with an 8051 microcontroller tagged on). 
However, these are small, slow, low-power microcontrollers - anything 
more will generate too much noise in the ADC.

When dreaming of "ideal" devices, it's important to understand some of 
the fundamentals of chip design.  There are many variations on the basic 
idea of sandwiching layers of silicon together, and many parameters - 
number of layers, size of features, types of doping, etc.  A process 
that is good for handling high quality analogue signals is very 
different from one for high speed, low voltage digital, which is 
different from one for high voltage digital, which is different for one 
for flash, and so on.  You can't combine such different applications on 
one die without greatly compromising the design (quality, speed, cost, 
power consumption, etc.).  Thus you can build a microcontroller with an 
ADC - it's either a fast microcontroller, or a good ADC, but not both. 
You can get an MPC55xx PowerPC microcontroller that's cheap, or that has 
a lot of flash, but not both.

>> QSPI:              with DMA controller for decent throughput
> QSPI is quite old architecture, which is copied from 68k. I guess, developing
> this architecture is unlikely. I guess, SPI implementation in PowerQUICC
> family is really fast.
> 

There are ColdFires with QSPI, and also MPC5xxx PPC-based 
microcontrollers with QSPI (although the details are slightly different 
from the original 68332).  It's a nice idea, though not the only way to 
get low-overhead SPI.

>> BDM:               6 pin (better yet, on-chip USB-BDM module)
> The debug port must work even in case of most of the target system is dead.
> BDM/JTAG has minimal requirements. It even doesn't need the alive system
> clock. For my guess, an on-chip USB-BDM module is useless due to USB needs
> working sophisticated stack and the other fragile resources.
> 

I agree with you here.  It's also worth noting that the BDM is used 
mainly during development and debugging (and possibly production testing 
and programming), so there is little point in making the BDM interface 
more sophisticated than it has to be - developers and testers can have 
external USB-BDM hardware.  If you want USB access to a BDM port, I'd 
recommend using FTDI's FT2232C device - it handles the USB access, and 
provides a synchronous serial port (as well as UART ports) that can be 
used to access the BDM, or JTAG, or other synchronous ports.


> 2. Common considerations:
> Traditionaly, the real-time control functionality is implemented by IO
> oriented low-cost microcontroller (or DSP), which is running small footprint
> RTOS or no RTOS at all. The computation-demanding high-level functionality is
> traditionally implemented by a communication oriented microcontroller.
> 

If the card requires complicated real-time IO as well as a "big" OS, it 
is probably worth splitting the tasks and having a "big" cpu for the 
"big" OS, and either small microcontrollers or programmable logic for 
the PWMs, ADCs, timers, etc.

mvh.,

David



> Coldfire family has excellent control capabilities together with quite
> powerful CPU core. Using a small footprint RTOS, the core resources are enough
> for entry-level networking, USB and other general purpose system functionality
> with moderate calculational demands. Look, for example, for NetBurner
> development kits.
> 
> For more calculational power, look at low-cost derivatives of PowerQuick
> family together with any low-cost control oriented microcontroller.
> 
> The alternative platform can be core+FPGA on single silicon.
> 
> 
> --- Bob Furber <[email protected]> wrote:
> 
>> I dream of finding a fast, low-power MPU with good control features, 
>> that can interface to lots of external memory to host a serious OS. I 
>> have yet to find such an animal.
>>
>> I see Freescale, NPX, ST and others tripping over themselves to come up 
>> with yet another or better 32-bit single-chip MPU. But, without external 
>> memory to host a serious OS.
>>
>> I salivate when I look at the MCF5553/4 with a plethora of dream I/O 
>> features ..but, with insufficient memory to host an OS.
>>
>> I look at the newer ColdFire external memory offerings with reasonable 
>> speed and low power features, capable of hosting an OS. But, it seems 
>> that they are i.MX wannabees, lacking serious control features (i.e., 
>> HC11 like technology to generate PWM signals).
>>
>> PowerPCs either offer mouth-watering control features with limited 
>> memory, or external memory with limited control features. And the PPC 
>> requires more instructions to do anything useful, making it a rather 
>> slow memory hog.
>>
>> i.MX and X-Scale offer speed, access to large memories, but little in 
>> the way of control features.
>>
>> ...and so on go the yabats.
>>
>> Every so often I dream about MOAM (Mother of all MPUs) and this is what 
>> it looks like:
>>
>> CPU:	           ColdFireV3 or Arm9 or 11
>>                     to enjoy Linux/uClinux support
>> Speed:	           > 200 MHz
>> DRAM Controller:   1.8v DDR/DDR2, 16 bit wide (FlexBus), 64MB or more
>> Flash Controller:  1.8v NOR, 16 bit wide, 64MB or more
>>                     1.8v NAND
>> Core Voltage:      1.8v or less
>> I/O Voltage:       3.3v. 5v tolerant
>> Power:             ultra low consumption, slow and sleep modes
>> eMIOS:             16+ ch (or 24 ch a la MPC5553)
>> eTPU:              16+ ch
>> SCI serial ports:  2+
>> USB:               1 device + 1 host
>> Ethernet:          10/100 with on-chip Phy
>> AtoD:              8 ch 12 bit, 100+ Ksps
>> QSPI:              with DMA controller for decent throughput
>>                     3+ chip selects
>>                     64+ MHz
>> GPIO module:       Unused pins -> GPIO
>> BDM:               6 pin (better yet, on-chip USB-BDM module)
>> Package:           As small as possible, 0.8mm BGA
>>
>> Nice-To-Haves
>> CAN                1+ Ch
>> SD card interface
>> Keypad interface
>> Graphic LCD interface
>>
>> Am I a voice in the wilderness?
>>
>> Bob Furber
>>

---
[email protected]              Send a post to the list.
[email protected]        Join the list.
[email protected]    Join the list in digest mode.
[email protected]     Leave the list.