Re: no activity on MCF5275 QSPI bus

David,

What are you using as a chip select?  SPI or QSPI data is transmitted when 
your chip select is asserted.  Either polarity can be used, but typically a 
chip select is asserted low.  Once the chip select is asserted, the SPI data 
transmission from the master begins.  You should set your scope to trigger 
on either the falling or rising edge of the signal you are using as your 
QSPI chip select (depends on your choice).  The SCK and QSPI data out should 
be transmitted during the time interval that the chip select is asserted. 
You will also need to select whether the data is supposed to be read on the 
rising or falling edge of the SCK.  This depends upon what the SPI slave is 
going to be expecting (as does the state selection for chip select 
assertion).

Hope this helps,

Luis


----- Original Message ----- 
From: "David van Geest" <[email protected]>
To: <[email protected]>
Sent: Thursday, March 13, 2008 3:05 PM
Subject: [ColdFire] no activity on MCF5275 QSPI bus


> Hi all,
>
> I'm having trouble with the QSPI on my M5275EVB.  I've written a test
> app that should give me some activity on the bus, according to the
> Programming Example in the manual (pg. 24-16).  With an oscope probe
> on pin 3 or 5 of J9 (SCK and QSDO, respectively), I don't see ANY
> activity - both pins stay at 3.3 V.
>
> The oscope works fine - I've run a whole lot of self-tests, and it
> shows similar signals just fine (e.g. the I2C on the same board).
>
> Some more background:  I'm running uClinux on the board.  I was trying
> to port the mcf_qspi driver, and when using my ported driver, was
> again not seeing any activity on the bus.  I decided to eliminate the
> driver as the source of the problem, and instead gave user apps R/W/E
> access to the QSPI registers using the PACR registers.
>
> When running the test app, all the QSPI registers seem to be written
> correctly.  I've included the test app source and sample program
> output below.  Note that I don't have a SPI device attached, which is
> why the received data is all 1s.
>
> At this point I'm thinking that either:
> a) I've missed something incredibly obvious and am going to look
> stupid by sending this email... :-)
> b) There's a hardware problem
>
> Can someone take a look at my test app code and help me eliminate that
> as a cause?
>
> Thanks!
> -David
>
> Test app code (reg definitions provided in a separate file):
> int main () {
> // I didn't want to do 12 bit transfers.... 16 bit instead
> // Also, set the baud rate to slowest setting with FF instead of 08
> QMR = 0x83FF;
> if (QMR == 0x83FF)
> printf("Step 1: QMR Write\n");
>
> QDLYR = 0x0404;
> if (QDLYR == 0x0404)
> printf("Step 2: QDLYR Write\n");
>
> QIR = 0xD00F;
> if (QDLYR == 0x0404)
> printf("Step 3: QIR Write\n");
>
> QAR = 0x0020;
> if (QDLYR == 0x0404)
> printf("Step 4: QAR Write\n");
>
> //while (1) {
> int i = 0;
> for (i = 0; i < 4; i++) {
> QDR = 0x7E00;
> }
> for (i = 0; i < 4; i++) {
> QDR = 0x7D00;
> }
> for (i = 0; i < 4; i++) {
> QDR = 0x7B00;
> }
> for (i = 0; i < 4; i++) {
> QDR = 0x7700;
> }
> printf("Step 5: QDR Command Write\n");
>
> QAR = 0x0000;
> printf("Step 6: QAR Write\n");
>
> u16 temp = 0x0000;
> for (i = 0; i < 16; i++) {
> temp = i;
> QDR = temp;
> }
> printf("Step 7: QDR Data Write\n");
>
> QWR = 0x0F00;
> printf("Step 8: QWR Write\n");
>
> QDLYR |= QDLYR_SPE;
> printf("Info: QDLYR is: %x\n", QDLYR);
> printf("Step 9: SPE Set\n");
>
>
> //wait until transfer is complete
> while (1) {
> printf("Step 10: Waiting...\n");
> temp = QIR & 0x0001;
> if (temp == 0x0001)
> break;
> }
>
> QAR = 0x0010;
> printf("Step 11: Write QAR\n");
> u16 receiveBuff[16];
> for (i = 0; i < 16; i++) {
> receiveBuff[i] = QDR;
> printf("Step 12: Received Data at %d is %x:\n",i,receiveBuff[i]);
> }
> //}
>
> printf("Done!\n");
>
> return(0);
>
> }
>
>
> Test app output:
> Step 1: QMR Write
> Step 2: QDLYR Write
> Step 3: QIR Write
> Step 4: QAR Write
> Step 5: QDR Command Write
> Step 6: QAR Write
> Step 7: QDR Data Write
> Step 8: QWR Write
> Info: QDLYR is: 8404
> Step 9: SPE Set
> Step 10: Waiting...
> Step 11: Write QAR
> Step 12: Received Data at 0 is ffff:
> Step 12: Received Data at 1 is ffff:
> Step 12: Received Data at 2 is ffff:
> Step 12: Received Data at 3 is ffff:
> Step 12: Received Data at 4 is ffff:
> Step 12: Received Data at 5 is ffff:
> Step 12: Received Data at 6 is ffff:
> Step 12: Received Data at 7 is ffff:
> Step 12: Received Data at 8 is ffff:
> Step 12: Received Data at 9 is ffff:
> Step 12: Received Data at 10 is ffff:
> Step 12: Received Data at 11 is ffff:
> Step 12: Received Data at 12 is ffff:
> Step 12: Received Data at 13 is ffff:
> Step 12: Received Data at 14 is ffff:
> Step 12: Received Data at 15 is ffff:
> Done!
> ---
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