Re: Linux x uClinux for ColdFires: what is the best for what?

John Bodnar wrote:
> Bob Furber wrote:
>> Commodity DDR and flash today comes in 0.8mm BGA packages
> 
> Yes, but these packages have split ball maps with a channel down the 
> middle, making them not much harder to route to than a TSOP.
> 
> We don't really have the luxury of being able to implement routing 
> channels like commodity memories.  If we were to go to sub-1 mm ball 
> pitch, we need to incorporate routing channels by depopulating balls, 
> and we'd likely end up in packages that are physically not much smaller 
> than what we're doing with 1 mm ball pitch today.
> 
> Cost matters, too, and it's less expensive to assemble a 1 mm pitch BGA 
> than it is a 0.8 mm pitch BGA.  For now, I most customers to whom I 
> talk, even for high-volume applications, aren't requesting sub-1 mm 
> pitches.  With our I/O counts in the 144 to 416 ball range, the coarser 
> 1 mm ball pitch seems to afford folks a little more leeway in escaping 
> our ball maps out to the rest of the PCB within a reasonable number of 
> layers.
> 
> That's not to say there aren't customers who are space constrained and 
> asking for smaller packages, though.  There just aren't that many of 
> them yet.
> 

I agree with that.  To build cards using 0.8 mm BGA, and correspondingly 
small chicken feed components, you need a much more expensive class of 
board production machine, putting the cards out of reach of smaller 
production companies.  I don't know how much of the market volume is 
covered by smaller companies, but 1 mm (and packages like the 360 bga 
with spaces in the middle) will appeal to a wider group than tiny BGA 
packages.  Best of all, offer both sizes!

>> While in this wishful thinking state of mind, I cannot help mentioning 
>> my Technicolor dream: A new, compact, fast, low powered MPC55xx with 
>> the PowerPC ripped out and replaced with a ColdFire or Arm core with 
>> FlexBus LPDDR/DDR2 interface ..and, oh, yes, don't forget USB Host & 
>> Device and 100/100 Ethernet and Phy ..all for < $50.
> 
> I don't see Ethernet PHYs getting integrated on-chip anymore.  They're 
> not conducive to being designed in sub-0.18 micron process technologies, 
> and they've recently become about as commoditized as RS-232 level shifters.
> 
> When I started work on the MCF5282, we were figuring $5 into the system 
> cost for the PHY.  We've now reduced that to $1 to $2 depending on the 
> target market.  That kind of cost erosion makes it difficult for us to 
> recoup the costs of developing the PHY and integrating it.
> 

I can see the difficulties in integrating a PHY (Ethernet or USB) on 
chip - different chip processes are optimal for different sorts of 
device.  There are also occasions when you would actively prefer a MII 
interface (such as for connecting to a switch chip).  But the big 
advantage for customers is that with a PHY on chip, you only have four 
lines for Ethernet, connected directly to a socket with magnetics - 
without the PHY, you have about 15 lines and an extra chip on the board. 
  With GbE, 480 MBit USB, and other faster peripherals, it's even worse 
as you are routing a fair number of parallel fast signals rather than 
just two differential pairs.

> BTW, I reserve the right to backtrack on this for Gbit Ethernet.  
> There's some commonality between a GbE PHY and things like PCIe and SATA 
> PHYs, which do get integrated, that might make this possible.  No 
> promises, just an observation.
>> b. Having tasted eTPU and MIOS on the MPC5xx, I got addicted.
> 
> eTPU...  We really have got the thumbscrews on you :-)
> 
> John
> 

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