Re: Linux x uClinux for ColdFires: what is the best for what?

David Brown wrote:

>> That's not to say there aren't customers who are space constrained and 
>> asking for smaller packages, though.  There just aren't that many of 
>> them yet.
> 
> I agree with that.  To build cards using 0.8 mm BGA, and correspondingly 
> small chicken feed components, you need a much more expensive class of 
> board production machine, putting the cards out of reach of smaller 
> production companies.  

I am sorry, although this perception is quite common, it is incorrect. 
If it is within our reach, it is within anybody's reach. We can get a 
fine pitch prototype board run for under $300 and we can get 4 to 6 of 
these protos (with 0.8mm bga flash and DDR ram plus a mess of discretes 
and a few support chips assembled for the cost of a stencil ($500) + 
$800. Not the budget of a low end hobbyist, but certainly within the 
reach of the smallest company.

It would be a shame for FSL to lag because of incorrect perceptions, 
even if they are shared by many of its clients. I would prefer to see 
FSL develop more cutting-edge products supported by app-notes with 
escaping and assembly tips to educate their more conservative clients.

> 	:
> I can see the difficulties in integrating a PHY (Ethernet or USB) on 
> chip - different chip processes are optimal for different sorts of 
> device.  There are also occasions when you would actively prefer a MII 
> interface (such as for connecting to a switch chip).  But the big 
> advantage for customers is that with a PHY on chip, you only have four 
> lines for Ethernet, connected directly to a socket with magnetics - 
> without the PHY, you have about 15 lines and an extra chip on the board. 
>  With GbE, 480 MBit USB, and other faster peripherals, it's even worse 
> as you are routing a fair number of parallel fast signals rather than 
> just two differential pairs.

You bring up some excellent points. And it is more than an extra 11 
lines. Adding that $1.80 Phy chip and half a dozen decoupling caps adds 
realestate for these parts and at least 50 additional traces. This has a 
significant impact on cost, size, EMI and signal quality. Depending on 
volume, it can cost in the order of $0.10 per part (i.e., a tiny smd 
cap) just to place it. And there is the extra board size. All of which 
translates to about 2 to 3 times the cost of the raw parts. In short, 
the off-chip phy ends up adding about $3 to $5 to the cost the finished 
product.

And, even though we hate to admit it, we all make mistakes. 1 in 100? 1 
in 1000? 1 in 10,000? The point is, the fewer signals and the fewer 
parts on a product, the smaller the chance of an error; an error that 
will cost time and money to locate and fix.

What I hear is that there are technical challenges to adding a Phy to a 
chip and this translate to higher costs. Perhaps FSL marketing is trying 
to compete on MPU cost. Personally, I would rather pay more for a nicely 
integrated MPU if it results in a reduction of the final product cost, 
size and power. And, this would apply to the power supplies too. For 
instance, the National DP83848 Phy generates an internal voltage 
on-chip. Flash chips have been doing this for ages. Why not the MCFxxxx?

>> BTW, I reserve the right to backtrack on this for Gbit Ethernet.  
>> There's some commonality between a GbE PHY and things like PCIe and 
>> SATA PHYs, which do get integrated, that might make this possible.  No 
>> promises, just an observation.
>>> b. Having tasted eTPU and MIOS on the MPC5xx, I got addicted.
>>
>> eTPU...  We really have got the thumbscrews on you :-)
>>
>> John
>>
> 
> ---
> [email protected]              Send a post to the list.
> [email protected]        Join the list.
> [email protected]    Join the list in digest mode.
> [email protected]     Leave the list.
> 
> 
> 

---
[email protected]              Send a post to the list.
[email protected]        Join the list.
[email protected]    Join the list in digest mode.
[email protected]     Leave the list.