Re: RE: DDR ram issue using MCF54450 @240Mhz

"nop head" <[email protected]> Wed, 17 Dec 2008 16:32:23 +0000
Newsgroups gmane.comp.hardware.motorola.microcontrollers.coldfire
Message-ID <[email protected]>
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Gregg,

I think turning on the cache allows burst accesses so if there is a problem
with those then it only shows up when the cache is enabled.

Regards, Chris

2008/12/17 Granville Gregg <[email protected]>

>  Hi all
>
>
>
> More to report my actual problem appears to be cache I have disabled icache
> and u-boot seems to be working as expected. If I type (icache on) the system
> locks up. Anyone know if this symptom is telling me something I need to look
> at such a layout other variables ect.
>
>
>
> Gregg
>
>
>  ------------------------------
>
> *Gregg GRANVILLE*
>
> Hardware Engineering Manager
>
> -------------------------------------------------------
>
> Tel 1 603.622.0212 / Fax 1 603.623.5623
>
> [email protected] / www.metronics.com
>
>
> -----------------------------------------------------------------------------------------
>
> *METRONICS* /// 30 Harvey Road // Bedford, NH 03110-6818 / US
>
> *From:* [email protected] [mailto:[email protected]]
> *On Behalf Of *Granville Gregg
> *Sent:* Wednesday, December 17, 2008 8:00 AM
> *To:* Granville Gregg
> *Subject:* [ColdFire] DDR ram issue using MCF54450 @240Mhz
>
>
>
> We have a MCF54450 running at a CPU CLK of 240Mhz. we are using U-Boot
> 1.2.0 our design is using 1 16 bit Flash a PC28F256P33B85 BGA64. We are
> executing code in Flash and have written a DDR-ram test walking ones and
> walking zeros and address and address this will run for days at a time
> billions and billions of writes and reads.
>
> When we move this to DDR-ram which is a MICRON MT47H64M8CF-3:F which we use
> two of on SD-16 through SD-31with SD_A0-SD_A13 and
>
> SD_CS
>
> SD_DM2
>
> SD_DQS2
>
> SD_DM3
>
> SD_DMQS3
>
>
>
> We cannot run code we are using the same settings as the Reference design
> the same chips. I have layed out the board with mentor and have put
> restraints in all of the lines to keep them within .4 inches in length.
>
>
>
> The symptoms are it either gets an exception out in space or locks up
> before it gets to NET: functions
>
>
>
> Anyone have any thoughts about the issue.
>
>
>
> Gregg
>
>
>
>
>
> [email protected] Send a post to the list. [email protected] the list.
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Gregg,<br><br>I think turning on the cache allows burst accesses so if there is a problem with those then it only shows up when the cache is enabled.<br><br>Regards, Chris<br><br><div class="gmail_quote">2008/12/17 Granville Gregg <span dir="ltr">&lt;<a href="mailto:[email protected]">[email protected]</a>&gt;</span><br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">









<div link="blue" vlink="purple" lang="EN-US">

<div>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">Hi all </span></p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">&nbsp;</span></p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">More to report my actual problem appears to be cache I have
disabled icache and u-boot seems to be working as expected. If I type (icache
on) the system locks up. Anyone know if this symptom is telling me something I need
to look at such a layout other variables ect.</span></p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">&nbsp;</span></p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">Gregg</span></p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">&nbsp;</span></p>

<div>

<div style="text-align: center;" align="center"><span style="color: rgb(31, 73, 125);">

<hr align="center" size="2" width="100%">

</span></div>

<p><b><span style="font-size: 10pt; color: rgb(40, 40, 40);">Gregg GRANVILLE</span></b><span style="color: rgb(31, 73, 125);"></span></p>

<p><span style="font-size: 10pt; color: rgb(40, 40, 40);">Hardware Engineering Manager</span><span style="color: rgb(31, 73, 125);"></span></p>

<p><span style="font-size: 10pt; color: maroon;">-------------------------------------------------------</span><span style="color: rgb(31, 73, 125);"></span></p>

<p><span style="font-size: 10pt; color: rgb(40, 40, 40);">Tel 1 603.622.0212 / Fax 1 603.623.5623</span><span style="color: rgb(31, 73, 125);"></span></p>

<p><span style="color: rgb(31, 73, 125);"><a href="mailto:[email protected]" target="_blank"><span style="font-size: 10pt; color: rgb(40, 40, 40);">[email protected]</span></a></span><span style="font-size: 10pt; color: rgb(40, 40, 40);"> / </span><span style="color: rgb(31, 73, 125);"><a href="http://www.metronics.com" target="_blank"><span style="font-size: 10pt; color: rgb(40, 40, 40);">www.metronics.com</span></a></span></p>


<p><span style="font-size: 10pt; color: maroon;">-----------------------------------------------------------------------------------------</span><span style="color: rgb(31, 73, 125);"></span></p>

</div>

<p><b><span style="font-size: 10pt; color: maroon;">METRONICS</span></b><span style="font-size: 10pt; color: rgb(31, 73, 125);"> </span><span style="font-size: 10pt; color: rgb(40, 40, 40);">/// 30 Harvey Road // Bedford,
NH 03110-6818 / US</span><span style="font-size: 11pt; color: rgb(31, 73, 125);"></span></p>

<div>

<div style="border-style: solid none none; border-color: rgb(181, 196, 223) -moz-use-text-color -moz-use-text-color; border-width: 1pt medium medium; padding: 3pt 0in 0in;">

<p><b><span style="font-size: 10pt;">From:</span></b><span style="font-size: 10pt;">
<a href="mailto:[email protected]" target="_blank">[email protected]</a> [mailto:<a href="mailto:[email protected]" target="_blank">[email protected]</a>] <b>On Behalf
Of </b>Granville Gregg<br>
<b>Sent:</b> Wednesday, December 17, 2008 8:00 AM<br>
<b>To:</b> Granville Gregg<br>
<b>Subject:</b> [ColdFire] DDR ram issue using MCF54450 @240Mhz</span></p>

</div>

</div><div><div></div><div class="Wj3C7c">

<p>&nbsp;</p>

<p>We have a MCF54450 running at a CPU CLK of 240Mhz. we are
using U-Boot&nbsp; 1.2.0 our design is using 1 16 bit Flash a PC28F256P33B85
BGA64. We are executing code in Flash and have written a DDR-ram test walking
ones and walking zeros and address and address this will run for days at a time
billions and billions of writes and reads.</p>

<p>When we move this to DDR-ram which is a MICRON
MT47H64M8CF-3:F which we use two of on SD-16 through SD-31with SD_A0-SD_A13 and</p>

<p>SD_CS</p>

<p>SD_DM2</p>

<p>SD_DQS2</p>

<p>SD_DM3</p>

<p>SD_DMQS3</p>

<p>&nbsp;</p>

<p>We cannot run code we are using the same settings as the
Reference design the same chips. I have layed out the board with mentor and
have put restraints in all of the lines to keep them within .4 inches in
length. </p>

<p>&nbsp;</p>

<p>The symptoms are it either gets an exception out in space
or locks up before it gets to NET: functions</p>

<p>&nbsp;</p>

<p>Anyone have any thoughts about the issue.</p>

<p>&nbsp;</p>

<p>Gregg </p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">&nbsp;</span></p>

<p><span style="font-size: 11pt; color: rgb(31, 73, 125);">&nbsp;</span></p>

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</div><div><div></div><div class="Wj3C7c">



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