QSPI B problem

Hello

I am working on the MPC565 processor.

I use the two QSPI A and QSPIB to transfert data to external chip.

I got a problem with the QSPI B.

The transfert with the QSPIA work well, I got correctly the  CS, CLK 
and DATA signal.
But on the QSPIB I only got the CLK. Signal  NO CS and NO DATA.

The initalisation are indentical between QSPIA and QSPIB.

Is there some extra register to init to work with QSPIB ?

Here is the init that i use.

Is there something wrong in my init. ?

Thanks in advance 


USIU.PDMCR.B.SLRC   = 0xF;

//---------------------------------------------------------------//
//----INIT GLOBAL REGISTER QSMCM A----//
//---------------------------------------------------------------//
QSMCM_A.QSMCR.R = 0;
QSMCM_A.QSMCR.B.STOP = 0; //utilisation normale des horloges
QSMCM_A.QSMCR.B.FRZ1 = 1; //arret du QSMCM lors d'un FREEZE 
QSMCM_A.QSMCR.B.SUPV = 1; //mode superviseur
QSMCM_A.QSMCR.B.IARB = 0; //unused

QSMCM_A.QSPI_IL.R = 0;
QSMCM_A.QSPI_IL.B.ILQSPI = 9;

//----------------------------------------------------------------//
INIT GLOBAL REGISTER QSMCM B ----//
//----------------------------------------------------------------//
QSMCM_B.QSMCR.R = 0;
QSMCM_B.QSMCR.B.STOP = 0; //utilisation normale des horloges
QSMCM_B.QSMCR.B.FRZ1 = 1; //arret du QSMCM lors d'un FREEZE 
QSMCM_B.QSMCR.B.SUPV = 1; //mode superviseur
QSMCM_B.QSMCR.B.IARB = 0; //unused

QSMCM_B.QSPI_IL.R = 0;
QSMCM_B.QSPI_IL.B.ILQSPI = 10

//-------------------------------------------------------------------
--//
//---- Configuration I/O  module QSMCM_A ----//
//-------------------------------------------------------------------
--//

//Choix des broches utilisées en tant que chip select (QPAPCS0 =
1) 
au lieu de GPIO (QPAPCS0 = 0)
QSMCM_A.PQSPAR.R = 0;
QSMCM_A.PQSPAR.B.QPAMISO = 1;	//signal SDI des composants externes
QSMCM_A.PQSPAR.B.QPAMOSI = 1;	//signal SDO des composants externes
QSMCM_A.PQSPAR.B.QPAPCS0 = 1;	//E2PROM	 	
QSMCM_A.PQSPAR.B.QPAPCS1 = 1;	//RTC	  	
QSMCM_A.PQSPAR.B.QPAPCS2 = 1;	//ADC_0C3	
QSMCM_A.PQSPAR.B.QPAPCS3 = 1;	//non utilisé
//DDRQS.B.QDDPCS0	=> chip select en sortie
QSMCM_A.DDRQS.R = 0;
QSMCM_A.DDRQS.B.QDDMOSI = 1 ;	//MOSI correspond au signal SDI des 
composants externes et donc doit être en sortie
QSMCM_A.DDRQS.B.QDDMISO = 0 ;	//MISO correspond au signal SDO des 
composants externes et donc doit être en entrée
QSMCM_A.DDRQS.B.QDDSCK  = 1;	//CLK maitre
QSMCM_A.DDRQS.B.QDDPCS0 = 1;    //E2PROM	PCS maitre
QSMCM_A.DDRQS.B.QDDPCS1 = 1;	//RTC		PCS maitre
QSMCM_A.DDRQS.B.QDDPCS2 = 1;	//ADC_0C3	PCS maitre
QSMCM_A.DDRQS.B.QDDPCS3 = 1;	//Non connecté

//Choix de la polarité des signaux (0: actif haut; 1: actif bas)
QSMCM_A.PORTQS.B.QDMISO = 1;
QSMCM_A.PORTQS.B.QDMOSI = 1;
QSMCM_A.PORTQS.B.QDSCK  = 1;
QSMCM_A.PORTQS.B.QDPCS0 = 0;
QSMCM_A.PORTQS.B.QDPCS1 =0;
QSMCM_A.PORTQS.B.QDPCS2 = 0;
QSMCM_A.PORTQS.B.QDPCS3 = 0;

//-------------------------------------------------------------------
--//
//---- Configuration I/O module QSMCM_B ----//
//-------------------------------------------------------------------
--//
//Choix des broches utilisées en tant que chip select (QPAPCS0 =
1) 
au lieu de GPIO (QPAPCS0 = 0)
QSMCM_B.PQSPAR.R = 0;
QSMCM_B.PQSPAR.B.QPAMISO = 1;	//signal SDI des composants externes
QSMCM_B.PQSPAR.B.QPAMOSI = 1;	//signal SDO des composants externes
QSMCM_B.PQSPAR.B.QPAPCS0 = 1;
QSMCM_B.PQSPAR.B.QPAPCS1 = 1;
QSMCM_B.PQSPAR.B.QPAPCS2 = 1;
QSMCM_B.PQSPAR.B.QPAPCS3 = 1;

//Choix direction des chip select (entree ou sortie) 
QSMCM_B.PQSPAR.R = 0;
QSMCM_B.DDRQS.B.QDDMOSI = 1 ;	//MOSI correspond au signal SDI des 
composants externes et donc doit être en sortie
QSMCM_B.DDRQS.B.QDDMISO = 0 ;	//MISO correspond au signal SDO des 
composants externes et donc doit être en entrée
QSMCM_B.DDRQS.B.QDDSCK  = 1;	//CLK maitre
QSMCM_B.DDRQS.B.QDDPCS0 = 1;    //ADC_OC1A	PCS maitre
QSMCM_B.DDRQS.B.QDDPCS1 = 1;    //ADC_OC1B	PCS maitre
QSMCM_B.DDRQS.B.QDDPCS2 = 1;    //DAC_OC2A	PCS maitre
QSMCM_B.DDRQS.B.QDDPCS3 = 1;    //DAC_OC2A	PCS maitre

//Choix de la polarité des signaux (0: actif haut; 1: actif bas)
QSMCM_B.PORTQS.B.QDMISO = 1;
QSMCM_B.PORTQS.B.QDMOSI = 1;
QSMCM_B.PORTQS.B.QDSCK  = 1;
QSMCM_B.PORTQS.B.QDPCS0 = 0;
QSMCM_B.PORTQS.B.QDPCS1 = 0;
QSMCM_B.PORTQS.B.QDPCS2 = 0;
QSMCM_B.PORTQS.B.QDPCS3 = 0;

    //configuration registre SPCR3
    QSMCM_A.SPCR3.B.LOOPQ = 0; //pas de wraparound
    QSMCM_A.SPCR3.B.HMIE = 0; //pas d'interruption lors d'un HALT ou 
MODF
    QSMCM_A.SPCR3.B.HALT = 0;
    
    //configuration registre SPCR3
    QSMCM_B.SPCR3.B.LOOPQ = 0; //pas de wraparound
    QSMCM_B.SPCR3.B.HMIE = 0; //pas d'interruption lors d'un HALT ou 
MODF
    QSMCM_B.SPCR3.B.HALT = 0;

    // mask IT SPI A
    USIU.SIMASK2.B.IMBIRQ9=1;
    // mask IT SPI B
    USIU.SIMASK2.B.IMBIRQ10=1;








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