RE: Work around for Machine check exception??

Hi,

RCPU can not access unaligned instructions. It's
instruction fetches are always aligned to 32 bit word
boundaries, because the address bits 30:31 are always
forced to "00" in non-compressed mode. 

You may inspect SRR0 and SRR1 register values to
determine the exception reason.

So if the "instruction" tables are not aligned in
memory, most likely the RCPU will get wrong
instruction codes, causing "unimplemented instruction"
exception- 
vector 0x1000 ..

Usual causes of the Machine Check in MPC5XX parts are:

1) Accessing internal memory space with unimplemented
location - like a gap in a module memory space - 
so called address error;

2) Accessing external address space not covered by any
CS region and the BUS Monitor is enabled, or
when CS region has protected for an access type - like
write to read only region
or external TEA pin assertion.
These conditions are signalled to the RCPU as a "data
error" indication.


Regards Alex.


--- Randall <[email protected]> wrote:

> 
> > Normally access to unaligned floating point
> operands should cause an
> > alignment exception, not a machine check.
> 
> That's true, but we/I are not talking about
> accessing unaligned FP operands, but
> rather unaligned FP instructions, which will cause a
> machine check.
> 
> Randall Young
> Senior Software Engineer
> NavCom Technology, Inc
> A John Deere Company
> 
> 



		
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