RE: TPU3 PWM glitch?

We are already limiting our lowest non-zero duty cycle to 5%, or 12.5us at 4kHz.  The PWM signal at this duty is solid.  When we drop below this value, zero is written to PWMHI.  The first period (250us after the last >5% pulse) with PWMHI=0 emits a 550ns pulse.  This pulse is seen regardless of where in the 250us period the write occurs.

Steve

-----Original Message-----
From: Eric McRae [mailto:[email protected]]
Sent: Thursday, August 04, 2005 10:10 AM
To: [email protected]
Subject: Re: [MPC500] TPU3 PWM glitch?


I think the thread has settled this but to be definitive, the 
documentation for the PWM function says that the minimum time between 
any two edges is 32 CPU clocks.  The problem as [email protected] 
mentioned, is that it takes the code and the TPU scheduling hardware 
some time to process each edge and schedule the next.  In the case of a 
low duty cycle pulse, the falling edge of the pulse may actually occur, 
or you might want it to occur, before the end of the code thread that 
creates it.  Typically this leads to the edge being delayed by 32K or 
64K TCR clocks.  In some cases, the first edge occurs but the match is 
not recognized so the thread never runs again.  A similar problem occurs 
near 100% duty cycle.

I wrote a high resolution PWM function a few years ago that could handle 
the short pulses down to the resolution of TCR1.  For the very short 
pulses, the function syncs with TCR1 and just counts its clicks.  It 
worked great but only because the customer didn't care about slight 
variations in the pulse period.  The function had to control both the 
rising and falling edges (in low duty cycle situations) in the firmware 
because there were other functions running on the same TPU and the 
associated latency would have stretched any hardware generated pulses.

Schroeder, Steven A. wrote:

> We are using a TPU3 channel in the MPC563 to generate a 4kHz PWM 
> signal.  Updating the duty cycle is accomplished by simply writing a 
> new PWMHI value and it operates very well.  Until now.  When the duty 
> cycle first becomes 0% we write 0 to PWMHI.  The first cycle at 0% 
> outputs a 550ns pulse; after that it stays low.
>
> The problem is that the device being driven does not like narrow 
> pulses such as this.  Has anyone seen this before?

-- 
Eric McRae, Electro-Logic Machines, Inc.
511 Root St., Port Townsend WA, 98368
Phone/Fax: 360.379.0969, http://www.elmi.com




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