RE: ??: RE: about MPC555 PCB

I have misunderstood your issue.  I thought you had lost BDM comms and my reply was based on that.  It appears your problem is that you are unable to boot from FLASH.  Please search the archive for advice on that as there are several places where you can go wrong.

Regards,
Allan

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of wupegasus
Sent: Monday, August 15, 2005 3:09 PM
To: [email protected]
Subject: Re: ??: RE: [MPC500] about MPC555 PCB


 thanks!

  As regarding to your advice, I have tried again, but failed.
  here I want to clarify the following:
1.I mean the board can enter into the BDM mode and still can be 
burned in the internal flash. After  removing the visionprobe 
connector, I think the board should run by itself and i can detect 
the signals in the TPU pins (  I have tried all the same program in 
my demo board from Windriver), but it failed.
2. in¡¡my board, I conect  RSTCFG to SRESET , as I do not entend the 
ROM and RAM, the data bus are not fetched out, so i try pulling 
RSTCFG high , it still does not work.

3.I have a pull-up on HREET by 4.7K ohm,  so  reduced it to 1K ohm. 
4.I use 4M xtl and make the  PLPRCR reg to 00910000, so i think the  
sys clock is 40MHz.

--- In [email protected], Dobbin Allan-r11834 
<Allan.Dobbin@f...> wrote:
> I don't think you can attach files through the group, but that¡¯s
OK as I don't particularly want to look through them all anyway.
> 
> There's a couple of things you say that are not clear and you will
have to verify:
> 
> 1) You say "the board doesn't work". Do you mean BDM
communications doesn't work? If it worked before you programmed but 
not now, its almost vertainly the DBPC/DBGC reset configuration 
locking out the BDM pins.  Instead of conecting RSTCFG to SRESET, 
try pulling it LOW - this forces reset cfg word to be read from the 
data bus, so ensure the relevant bits (9,10,11) are in the correct 
state i.e. all LOW or 010.  If that doesn't work, try pulling RSTCFG 
high which means it gets reset word from shadow.
> 
> 2) You say you "force sys clock to 40MHz".  I don't know what you
mean by 'force', but make sure you are using either a 4M or 20Mhz 
xtal or osc and that the MODCLK pins are set correctly.  Look at the 
CLKOUT signal to verify the PLL has locked.  If things are set 
correctly, you'll usually have a 20MHz clock after reset.
> 
> 3) If you have a pull-up on HREET, try reducing it to 1K ohm.
> 
> 4) Check all your BDM connections and refer to the Freescale App
note "MPC500 Family Background Debug Mode".

  I still remember your first answer ¡°Assuming you clocks, power 
and reset is/were correct, I suspect you've programmed the reset 
config word in shadow." 

 


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