RE: Queued SCI with Interrupts on MPC555

This morning I got up, fired up the machine, and ran this again. Now it does
not work..., it ran several times last night but after being powered down
all night, it does not. I must have had the hardware in some state that
allowed it to work, which I can't duplicate this morning. So, I'm still
trying to figure out a combination of "start transmit" code and ISR that
will keep the queue transmitting reliably. Does anyone have an suggestions
about what is wrong/missing from this code?

 

Thanks,

 

Dave

 

 

  _____  

From: [email protected] [mailto:[email protected]] On Behalf Of
David Eicher
Sent: Wednesday, December 07, 2005 6:58 PM
To: [email protected]
Subject: RE: [MPC500] Queued SCI with Interrupts on MPC555

 

Hi Allan,



Well, I made a few adjustments, and found a combination that seems to work.
The first group of code here is the code that initiates the transmit (QBHEI
is already set). The second group of code is the code of the ISR that keeps
the transmit running. I need to experiment more and verify that I actually
need the wrap bit set, I doubt it because I'm not actually wrapping. I'll
keep working at it. Thanks again for your help.



Dave



--------------------------------------------------------- start transmit
-----------------------------------------------------------------



            for (i=0;i<16;i++) scratch[i] = 'a';

            

            ioctl(QSMCM_QSCI1, QSCI_ENABLE_TX_WRAP, SCI_ENABLE); 

            ioctl(QSMCM_QSCI1, QSCI_WRITE_QUEUE_TX_SIZE, 16);

            

            /* read SR with TC set */

            while(!(ioctl(QSMCM_SCI1, SCI_GET_FLAGS, SCI_TX_COMPLETE))) {;}


            



              /* fill the whole buffer */  

              write(QSMCM_QSCI1, QUEUE_TOP_HALF, scratch, 16);



              /* Clear top half and bottom half flags QTHE/QBHE */

              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS, QSCI_TX_TOP_HALF);

              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS, QSCI_TX_BOT_HALF);

            

              /* Set queued enable flag in control register QTE */


              ioctl(QSMCM_QSCI1, QSCI_QUEUE_TX, SCI_ENABLE);

              /* Set QSCI transmit enable flag in control register TE */

              ioctl(QSMCM_SCI1, SCI_TRANSMITTER, SCI_ENABLE);





--------------------------------------------------------- ISR
----------------------------------------------------------------------------
---



  if (ioctl(QSMCM_QSCI1, QSCI_GET_QUEUE_FLAGS, QSCI_TX_BOT_HALF))

  {

      ioctl(QSMCM_QSCI1, QSCI_ENABLE_TX_WRAP, SCI_ENABLE); 

              ioctl(QSMCM_QSCI1, QSCI_WRITE_QUEUE_TX_SIZE, 16);

                                    

              /* read SR with TC set */

              while(!(ioctl(QSMCM_SCI1, SCI_GET_FLAGS, SCI_TX_COMPLETE)))
{;}  



              for (i=0;i<14;i++) scratch[i] = 'c';

              scratch[14] = (u_char)13;

              scratch[15] = (u_char)10;

              write(QSMCM_QSCI1, QUEUE_TOP_HALF, scratch, 16);



              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS, QSCI_TX_TOP_HALF);
/* clear QBHE */

              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS, QSCI_TX_BOT_HALF);

            

              if (data[0]< 6)  /* stop after 5 interrupts */

              {

                ioctl(QSMCM_QSCI1, QSCI_QUEUE_TX, SCI_ENABLE);

                ioctl(QSMCM_SCI1, SCI_TRANSMITTER, SCI_ENABLE);

              }

              else

              {

                ioctl(QSMCM_QSCI1, QSCI_QUEUE_TX, SCI_DISABLE);

                ioctl(QSMCM_SCI1, SCI_TRANSMITTER, SCI_DISABLE);

            }

   }











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