RE: Queued SCI with Interrupts on MPC555

"David Eicher" <[email protected]>
Newsgroups gmane.comp.hardware.motorola.microcontrollers
Message-ID <[email protected]> 
Hi Allan,

 

Using mixed mode did work, I was able to see the context restore at the end
of the ISR. So now I have confidence that all the registers are being saved
and then restored upon exit of the ISR.

 

Thanks again,

 

Dave

 

 

  _____  

From: [email protected] [mailto:[email protected]] On Behalf Of
Dobbin Allan-r11834
Sent: Thursday, December 08, 2005 8:28 AM
To: [email protected]
Subject: RE: [MPC500] Queued SCI with Interrupts on MPC555

 

I don't know how to save the intermediate files, but within the
debugger, select 'Mixed' so you can see source plus assembly and then
step into the ISR so you can see the code in the debug window.  If you
are struggling to see the interrupt handling code before your ISR, set a
breakpoint within your ISR and step until you exit your ISR (in mixed
format) and you will be back in CW's interrupt handler.

If the interrupt is getting to where it should, chances are that you've
set up CW correctly.  Perhaps you are getting a 2nd interrupt from
another source while you're in the routine - if you've enabled nested
interrupts but not set the code to handle that properly, you could get
into trouble there. For now, don't set MSR[EE] within your ISE so nested
interrupts are avoided.

To answer your questions from last night:

- I read SC1SR and SC1DR to clear the (non-queued) status flags as I
seem to remember that FE, PF, etc will clear QRE. Perhaps I'm confusing
things here as this applies only to queued reception, so forget this for
now.

- to start transmission, yes, I set QBHEI and call my TxISR function.

- Within TxISR, yes I'm only using bottom half interrupts, so I don't
even bother checking QBHE as it's my only SCI interrupt source (actually
I'm also using rx ints, so my external_interrupt handler checks to see
if an rx int is pending and if not, it assumes it's a QBHE interrupt and
jumpt to TxISR).  Within TxISR, first I write 16 bytes into the tx
queue, then I clear both QBHE and QTHE. Remember to clear these you read
and then write 0, so the following works:

QSMCM.QSCI1SR.B.QBHE = 0;      /* clear status flag by reading then
writing zero. This also clears SIPEND */ 
QSMCM.QSCI1SR.B.QTHE = 0;      /* clear status flag by reading then
writing zero. This also clears SIPEND */

Finally within TxISR, I set QTE again as it clears after queue is
transmitted (IMPORTANT).  I do NOT enable wrap since I don't want to
transmit old data if my ISR isn't fast enough, instead the tx would just
go dead for a short period.

I don't like to put source code up on the group, but I've went ahead and
put up my init and ISR code.  For the init code, it also enables an rx
interrupt queue, so your going to have to remove that part yourself. Let
me know if this works for you.

Regards,
Allan



/* Enable the QSCI for IBE comms with interrupts. */
/* Receiver queued interrupts enabled, transmitter disabled until
polled. */
/* External interrupts still have to be enabled externally to this
function */
/***********************************************************************
***/
      QSMCM.QSMCR.R = 0x0000;            /* Supr=off, Normal clk, FRZ =
off, */
      QSMCM.QDSCI_IL.B.ILDSCI = QSCI_LEVEL;      /* Set QSCI interupt
priority */
      QSMCM.SCC1R1.R = 0x0000;      /* Normal SCI1 operation, CMOS,
no parity, 8 data, no intrrupts, disable Rx/Tx */
      QSMCM.SCC1R0.R = RS485_BAUD;      /* set baud rate */

      temp16 = QSMCM.SC1SR.R;            /* Read the status register */
      temp16 = QSMCM.QSCI1SR.R;      /* Read the Q status register */
      QSMCM.QSCI1SR.R = 0x0000;      /* CLEARS qth,qtbh, */

      QSMCM.QSCI1CR.R = 0x002f;      /* Enable Rx queue (Tx queue off
until polled), no queue wrap, Tx 16 bytes long */
      QSMCM.QSCI1CR.B.QTHFI = 1;
      QSMCM.QSCI1CR.B.QBHFI = 1;      /* Enable Rx interrupts */
      QSMCM.QSCI1CR.B.QBHEI = 0;      /* Disable Tx interrupts for now
*/

      QSMCM.SCC1R1.B.RE = 1;            /* Rx enable */
      QSMCM.SCC1R1.B.TE = 1;            /* Tx enable */


/**************************************************************/
/* later when I'm ready to transmit -this is actually in a timer
interrupt */
/**************************************************************/
      QSMCM.QSCI1CR.B.QBHEI = 1;      /* enable Tx interrupts */
      TxQueISR ();      /* Start the transmitter interrupts going */



/***********************************************************************
********
FUNCTION        : void TxQueISR
PURPOSE         : Interrupt service routine for SCI queued transmitter.
Pulls data from Tx.buffer.
INPUTS NOTES    : none
RETURNS NOTES   : none
GENERAL NOTES   : This routine is called by interrupt when the QSCI
transmit buffer
                  is empty. The routine puts the next 16 characters from
the Tx
                  buffer into the QSCI queue. If there are less than 16
characters
                  to transmit, the transmitter is disabled. This works
since there
                  will always be 16 dummy characters padded onto the end
of the message.
************************************************************************
*******/
void TxQueISR (void)
{
      if (Tx.count < 16)      /* only transmit 16 bytes at a time.
There will always be at least 16 dummy bytes on the end of a message */
      {
            Tx.count = 0;
      
            QSMCM.QSCI1SR.B.QBHE = 0;      /* clear status flag by
reading then writing zero. This also clears SIPEND */
            QSMCM.QSCI1SR.B.QTHE = 0;      /* clear status flag by
reading then writing zero. This also clears SIPEND */
            QSMCM.QSCI1CR.B.QTE = 0;      /* Disable transmitter -
finished transmitting current messages */
            QSMCM.QSCI1CR.B.QBHEI = 0;            
      }
      else
      {
            Tx.count -= 16;                  /* decrement character
count */

            /* write to tx queue - this also clears the TC bit */
            /* avoided loop for speed */      
            QSMCM.SCTQ[0].R = Tx.buffer[Tx.next++];            /* get
character from buffer */
            QSMCM.SCTQ[1].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[2].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[3].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[4].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[5].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[6].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[7].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[8].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[9].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[10].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[11].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[12].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[13].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[14].R = Tx.buffer[Tx.next++];
            QSMCM.SCTQ[15].R = Tx.buffer[Tx.next++];

            QSMCM.QSCI1SR.B.QBHE = 0;      /* clear status flag by
reading then writing zero. This also clears SIPEND */ /**ad as above,
may not be rqd */
            QSMCM.QSCI1SR.B.QTHE = 0;      /* clear status flag by
reading then writing zero. This also clears SIPEND */
            QSMCM.QSCI1CR.B.QTE = 1;      /* SETS QTE Transmit
ENABLE - appears to clear after queue is completed */
      }

}      /* end of TxQueISR */





-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf
Of David Eicher
Sent: Thursday, December 08, 2005 9:12 AM
To: [email protected]
Subject: RE: [MPC500] Queued SCI with Interrupts on MPC555


Hmmm, okay, it works if I take the test  out that checks to see if I've
gotten 5 interrupts       if (data[0]< 6)  /* stop after 5 interrupts */

With that removed and just setting QTE and TE it transmits reliably and
continuously. I'm beginning to think my intermittent behaviour could be
related to not saving context and restoring context. The CW pragma
interrupt is suppose to get that done for me. I don't know how to check
and see if it is working. Does anyone know how to make CW save
intermediate files so I can see the assembly source it is generating?



Thanks,



Dave





  _____  

From: [email protected] [mailto:[email protected]] On Behalf
Of David Eicher
Sent: Thursday, December 08, 2005 6:51 AM
To: [email protected]
Subject: RE: [MPC500] Queued SCI with Interrupts on MPC555



This morning I got up, fired up the machine, and ran this again. Now it
does not work..., it ran several times last night but after being
powered down all night, it does not. I must have had the hardware in
some state that allowed it to work, which I can't duplicate this
morning. So, I'm still trying to figure out a combination of "start
transmit" code and ISR that will keep the queue transmitting reliably.
Does anyone have an suggestions about what is wrong/missing from this
code?



Thanks,



Dave





  _____  

From: [email protected] [mailto:[email protected]] On Behalf
Of David Eicher
Sent: Wednesday, December 07, 2005 6:58 PM
To: [email protected]
Subject: RE: [MPC500] Queued SCI with Interrupts on MPC555



Hi Allan,



Well, I made a few adjustments, and found a combination that seems to
work. The first group of code here is the code that initiates the
transmit (QBHEI is already set). The second group of code is the code of
the ISR that keeps the transmit running. I need to experiment more and
verify that I actually need the wrap bit set, I doubt it because I'm not
actually wrapping. I'll keep working at it. Thanks again for your help.



Dave



--------------------------------------------------------- start transmit
-----------------------------------------------------------------



            for (i=0;i<16;i++) scratch[i] = 'a';

            

            ioctl(QSMCM_QSCI1, QSCI_ENABLE_TX_WRAP, SCI_ENABLE); 

            ioctl(QSMCM_QSCI1, QSCI_WRITE_QUEUE_TX_SIZE, 16);

            

            /* read SR with TC set */

            while(!(ioctl(QSMCM_SCI1, SCI_GET_FLAGS, SCI_TX_COMPLETE)))
{;}


            



              /* fill the whole buffer */  

              write(QSMCM_QSCI1, QUEUE_TOP_HALF, scratch, 16);



              /* Clear top half and bottom half flags QTHE/QBHE */

              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS,
QSCI_TX_TOP_HALF);

              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS,
QSCI_TX_BOT_HALF);

            

              /* Set queued enable flag in control register QTE */


              ioctl(QSMCM_QSCI1, QSCI_QUEUE_TX, SCI_ENABLE);

              /* Set QSCI transmit enable flag in control register TE */

              ioctl(QSMCM_SCI1, SCI_TRANSMITTER, SCI_ENABLE);





--------------------------------------------------------- ISR
------------------------------------------------------------------------
----
---



  if (ioctl(QSMCM_QSCI1, QSCI_GET_QUEUE_FLAGS, QSCI_TX_BOT_HALF))

  {

      ioctl(QSMCM_QSCI1, QSCI_ENABLE_TX_WRAP, SCI_ENABLE); 

              ioctl(QSMCM_QSCI1, QSCI_WRITE_QUEUE_TX_SIZE, 16);

                                    

              /* read SR with TC set */

              while(!(ioctl(QSMCM_SCI1, SCI_GET_FLAGS,
SCI_TX_COMPLETE))) {;}  



              for (i=0;i<14;i++) scratch[i] = 'c';

              scratch[14] = (u_char)13;

              scratch[15] = (u_char)10;

              write(QSMCM_QSCI1, QUEUE_TOP_HALF, scratch, 16);



              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS,
QSCI_TX_TOP_HALF);
/* clear QBHE */

              ioctl(QSMCM_QSCI1, QSCI_CLEAR_QUEUE_FLAGS,
QSCI_TX_BOT_HALF);

            

              if (data[0]< 6)  /* stop after 5 interrupts */

              {

                ioctl(QSMCM_QSCI1, QSCI_QUEUE_TX, SCI_ENABLE);

                ioctl(QSMCM_SCI1, SCI_TRANSMITTER, SCI_ENABLE);

              }

              else

              {

                ioctl(QSMCM_QSCI1, QSCI_QUEUE_TX, SCI_DISABLE);

                ioctl(QSMCM_SCI1, SCI_TRANSMITTER, SCI_DISABLE);

            }

   }











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