Re: mpc555 memory mapping

Hi Randall,

Thanks for the info. Let me see if I understand this.

1) 555 base address = 0x000000
2) XRAM mapped to 0x400000 on CS1
3) ETRE=1,IP=1,OERC=0 --> smaller exception table at 0x000000
4) When debugging, dual map address 0x000000 to 0x400000 (CS1)

When interrupts occur, exception vector fetch from 0x000000+offset
will actually be from XRAM 0x400000+offset? This will work even if
internal flash is disabled?

That would be great. I have found another way to map the 555 and XRAM
to separate 4MB regions, but it requires different APPCONFIG.H and
EXCTABLE.ASM files for the DEBUG and INTFLASH targets, which is very
inconvenient. Do you use QUICKSTART?

Joe

--- In [email protected], "Randall Young" <ryoung@n...> wrote:
>
> 
> > I'm wondering if someone can help me with a memory mapping question.
> >
> > We've got a custom 555 board with 4MB of external RAM, all on one CS.
> > When running from internal flash, the base address of the 555 is
> > 0x000000 and the external RAM is mapped to address 0x400000. When
> > we're debugging, we disable the internal flash and map the external
> > RAM to address 0x000000. In this debug configuration, we can't access
> > external RAM addresses from 0x2FC000 to 0x3FFFFF because those are
> > assigned to internal 555 registers and internal RAM.
> 
> Check out the DME bit in the DMBR.  That will allow you to keep your
> external RAM configured at 0x400000, and also map the internal flash
address
> range (at 0x0) on top of it.  Special registers and internal RAM
will not be
> redirected.
> 
> Randall Young
> Senior Software Engineer
> NavCom Technology, Inc.
> A John Deere Company
> 
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