RE: PLL not locking

11 MHz is the limp clock.
 
this sounds as if you are not holding HRESET long enough. If the PLL is
not locked when HRESET negates, then the MCU will not run on the PLL as
the system clock.
 
Your software should check to make sure that the system clock is the PLL
(SCCR[BUCS]=0) and not the limp clock (SCCR[BUCS]=1). If the system
clock is the limp clock, then software should check to see if the PLL is
locked (PLPRCR[SPLS]=1).
 
if the PLL is truly not locking, then it would indicate that there is
excessive noise on the VDDSYN or the crystal is not stable. The MPC56x
devices are fairly robust for noise immunity on VDDSYN. You should check
the layout of your board around the VDDSYN/VSSSYN and the layout of the
crystal oscillator circuitry. We have seen customers improperly run very
high current, switching signals across the crystal circuitry that caused
the crystal to have glitches that cause problems for the PLL to
synchronize to. VDDSYN and the oscillator circuitry should have a clean
layout, free from excessive noise. 
 
randy
 

	-----Original Message-----
	From: [email protected] [mailto:[email protected]] On
Behalf Of pradeep karosiya
	
	
	Hi Allan
	  Thanks for the reply, i'm checking the status of SPLS bit
(sorry i wrote SPLSS bit by mistake). I'm using initialization files
provided by Metrowerks Codewarrior. The MODCLK is 010 and PLPRCR is
initialized to 0x00900000
	  I'm getting the CLKOUT as 11 MHz and system is strucking in
the while loop which is waiting for PLL lock (setting of SPLS bit).
Please suggest something.
	   
	  Thanks and Regards
	  Pradeep



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