Re: introduce Delay in MPC565 !!

Its quite possible, I implement the 'c' clock function basically by
reading the timebase, and then muliplying the result by a scale factor
based on the time base clock frequency and the units I require for the
clock_t type. I typically use ns becuase I use the same routine on a
number of different powerpc, and they all tend to clock from slightly
different sources, memory clock, cpu clock etc.
 
The following code makes an external call to get this constant scale
factor, which it then caches locally. Note, I define clock_t as a 64 bit
unsigned.
 
.globl clock ; read time base convert to clock_t
.globl GetTimeBase ; read the time base (raw units)
.extern OS_GetTimeBaseConstant

.sbss
.type _clockscale,@object ; allows elf debuggers to find it
.size _clockscale,4 ; and how big it is
.align 4

_clockscale: .space 4 ; reserve storage


.section .text,4,c

StackFrame = 8
StackLR = StackFrame+4

GetTimeBase:

; function obtains an atomic copy of the time base which is returned
; in r3, r4.
; uses r12, EABI volatile register 

mftbu r3 ; get high word
mftb r4 ; and low word
mftbu r12 ; and high word again

cmpl 0,0,r3,r12 ; check if wrapped while reading
bne- GetTimeBase ; predict not taken
blr ; back to caller


clock:

; read time base, convert into clock_t by using scale factor 
; returns result in r3,r4
; uses EABI volatiles r12 and r11

addis r11,r0,_clockscale@ha ; use absolute addressing
lwz r11,_clockscale@l(r11) ; to read 
cmpi 0,0,r11,0 ; test for zero
bne+ clock1 ; predict taken

; we have no clock scale value, perform a system call to obtain in r3

stwu r1,-StackFrame(r1) ; create a stack frame
mfspr r0,lr
stw r0,StackLR(r1) 
bl OS_GetTimeBaseConstant ; get time constant
lwz r0,StackLR(r1) ; distroy stack frame
mtspr lr,r0
addi r1,r1,StackFrame
addis r11,r0,_clockscale@ha ; reload address
stw r3,_clockscale@l(r11) ; save it off for next time
or r11,r3,r3 ; and get it in r11

clock1: 

; read timebase registers, obtaining an atomic set of results 
; in r3(hi) and r4 (lo)

mftbu r3
mftb r4
mftbu r12

cmpl 0,0,r3,r12 ; check if wrapped while reading
bne- clock1 ; predict not taken

; perform the 64 bit by 32 bit multiply (result is LOW order 64 bits
; of the 96 bit result)

mullw r0, r11, r3
mulhwu r3, r11, r4
add r3, r3, r0 ; high result
mullw r4, r11, r4 ; low result

blr; return to the caller




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