Questions on external RAM access timing parameters on 556

Hi, all

I'm starting a hardware design using the 56Mhz 556. Checked the 
Freescale eval board design and analyzed its RAM timing (don't have the 
code or an actual board). First time working with SSRAMs.

Have 2 concerns:

1) data hold time on reads is min 2 ns. The Cypress 1338 RAM holds it 
2nS min. Is it assumed that data flight time assures margin? My design 
(like the eval board) will have a very short RAM-to-566 trace length, 
so this time will be "short".

2) The 566 hold time for WE0-3 has no minimum specified. I assume it 
goes high no earlier than the CLKOUT rising edge. The CY7C1338 needs at 
least 0.5nS hold time on this strobe. Again, is this assumed to be 
assured by flight time?

Thanks for any advice on this. 





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