RE: ENGCLK

"Dees Randy-rsaf30" <[email protected]> Wed, 26 Sep 2007 07:06:58 -0700

Newsgroups	gmane.comp.hardware.motorola.microcontrollers
Message-ID	<3CCF040BDA7E0A46B3DF0F6B4741630A025C342D@az33exm23.fsl.freescale.net>

There is no way to evenly divide 66 MHz by 4. your best bet is to lower
the system frequency to 64 MHz, which is a multiple of 4 MHz, if the
ENGCLK needs to be exactly 4.0 MHz.

________________________________

From: [email protected] [mailto:[email protected]] On Behalf
Of [email protected]
Sent: Wednesday, September 26, 2007 8:04 AM
To: [email protected]
Subject: [MPC500] ENGCLK

With an MPC563 running with fsys at 66MHz, is there any way to get a
4MHz ENGCLK? The best ENGDIV can to is 4.125MHz-is there another
divider somewhere that I have missed?

Steve

.

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