RE: AN2789 - MPC5500 Configuration and Initialization
"Dobbin Allan" <[email protected]> Wed, 7 Jan 2009 10:54:07 -0700
| Newsgroups | gmane.comp.hardware.motorola.microcontrollers |
|---|---|
| Message-ID | <4147ED8B92A864498825C07E53594E4A03FAFDC4@az33exm20.fsl.freescale.net> |
--goc8EalXSYMdGKmSCmzmmebA8C7divQvsSUA08A Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit I am not familiar with any of these specific files, but will try to answer some from a general perspective: cache - correct, cache is disabled out of reset. To enable cache you have to write the L1CSR0 to turn on the cache, plus you have to make specific memory cachable within its MMU setting - note that some of the MMU settings already be cachable out of reset. (1) Why would you want to enable cache - cache is only one access cycle so your code will executes faster. Note that Idd will increase when you use the cache. (2) There is no need to check L1CFG0 - this is constant data for each part in the family and merely confirms the size of the cache. FMPLL - this allows you to set you sysclk to your desired rate. (1) Changing PREDIV and MFD forces the PLL to re-lock which means the frequency swings either side of the final locking frequency. If you are setting the max sysclk i.e. 132, the sysclk would swing above that value briefly during the locking phase and its possible the part could fail if the frequency is too high. To prevent this, you get it to lock with the post divider (RFD) at +1 (i.e. divide by 2) i.e. 66MHz so that max freq is not violated. Once the PLL has locked, you set RFD to desired value to get desired frequency (i.e. 132M) and since the post divider is outside of the VCO loop, there is no relocking or overshoot during this second step. (2) can't think of a good reason why cache is inhibited here. SRAM ECC - you HAVE to init the SRAM after a power up (not required after a RESET) by performing a 64-bit write. Failing to do so means that the 72-bit SRAM word (64-bit data plus 8-bit ECC checksum) has incorrect checksum and any accesses other than a 64-bit write will cause it to fail and generate an exception or bus error. Not initialising the SRAM doesn't mean bits will flip, it means you simply cannot read or write the SRAM. cfg_FLASH - the Flash comes out of reset with maximum wait-states. Refer to the ref manual, but even at max sysclk frequency, maximum wait states are not required, so to get improved performance from the flash, you would set the minimum possible wait-states for your operating frequency. cfg_MMU - I'm not familiar with the details of the files but reasons for changing MMU would be to enable cache or VLE for specific regions, to set memory blocks for external memory or even to re-arrange the entire memory map to suit your own prefferential memory map if so desired. - Allan ________________________________ From: [email protected] [mailto:[email protected]] On Behalf Of stevenaschroeder Sent: Wednesday, January 07, 2009 11:24 AM To: [email protected] Subject: [MPC500] AN2789 - MPC5500 Configuration and Initialization I have been experimenting with Freescales, MPC5500 initialization code and wonder if someone could clarify a few things for me. Running down the list of configuration functions: cfg_CACHE - If I understand, the cache is not active out of reset, so this simply enables it. (1) Why wouldn't you want to do this? (2) If you know the particular part has cache, is there a need to check L1CFG0? cfg_FMPLL - The Reference refers to setting the clock with your final values with RFD+1, then reducing RFD after lock. (1) Why would you want to set the clock to a series of rates, waiting for locks, such as the 132MHz example? (2) What is the significance of inhibiting the cache? cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably bad--more than just loosing ECC, it may flip bits incorrectly on read? cfg_FLASH - What has changed at this point to allow less internal flash wait states? cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any reason to worry about this? Thanks in advance. Steve [Non-text portions of this message have been removed] --goc8EalXSYMdGKmSCmzmmebA8C7divQvsSUA08A Content-Type: text/html; charset=US-ASCII Content-Transfer-Encoding: 7bit <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <html> <head> </head> <body style="background-color: #ffffff;"> <!--~-|**|PrettyHtmlStartT|**|-~--> <div id="ygrp-mlmsg" style="width:655px; position:relative;"> <div id="ygrp-msg" style="width: 470px; margin:0; padding:0 25px 0 0; float:left; z-index:1;"> <!--~-|**|PrettyHtmlEndT|**|-~--> <div id="ygrp-text"> <p>I am not familiar with any of these specific files, but will try to<br> answer some from a general perspective:<br> <br> cache - correct, cache is disabled out of reset. To enable cache you<br> have to write the L1CSR0 to turn on the cache, plus you have to make<br> specific memory cachable within its MMU setting - note that some of the<br> MMU settings already be cachable out of reset. (1) Why would you want<br> to enable cache - cache is only one access cycle so your code will<br> executes faster. Note that Idd will increase when you use the cache.<br> (2) There is no need to check L1CFG0 - this is constant data for each<br> part in the family and merely confirms the size of the cache.<br> <br> FMPLL - this allows you to set you sysclk to your desired rate. (1)<br> Changing PREDIV and MFD forces the PLL to re-lock which means the<br> frequency swings either side of the final locking frequency. If you are<br> setting the max sysclk i.e. 132, the sysclk would swing above that value<br> briefly during the locking phase and its possible the part could fail if<br> the frequency is too high. To prevent this, you get it to lock with the<br> post divider (RFD) at +1 (i.e. divide by 2) i.e. 66MHz so that max freq<br> is not violated. Once the PLL has locked, you set RFD to desired value<br> to get desired frequency (i.e. 132M) and since the post divider is<br> outside of the VCO loop, there is no relocking or overshoot during this<br> second step. (2) can't think of a good reason why cache is inhibited<br> here.<br> <br> SRAM ECC - you HAVE to init the SRAM after a power up (not required<br> after a RESET) by performing a 64-bit write. Failing to do so means<br> that the 72-bit SRAM word (64-bit data plus 8-bit ECC checksum) has<br> incorrect checksum and any accesses other than a 64-bit write will cause<br> it to fail and generate an exception or bus error. Not initialising the<br> SRAM doesn't mean bits will flip, it means you simply cannot read or<br> write the SRAM.<br> <br> cfg_FLASH - the Flash comes out of reset with maximum wait-states.<br> Refer to the ref manual, but even at max sysclk frequency, maximum wait<br> states are not required, so to get improved performance from the flash,<br> you would set the minimum possible wait-states for your operating<br> frequency.<br> <br> cfg_MMU - I'm not familiar with the details of the files but reasons for<br> changing MMU would be to enable cache or VLE for specific regions, to<br> set memory blocks for external memory or even to re-arrange the entire<br> memory map to suit your own prefferential memory map if so desired.<br> <br> - Allan<br> <br> ____________<wbr>_________<wbr>_________<wbr>__<br> <br> From: <a href="mailto:MPC500%40yahoogroups.com">MPC500@yahoogroups.<wbr>com</a> [mailto:<a href="mailto:MPC500%40yahoogroups.com">MPC500@yahoogroups.<wbr>com</a>] On Behalf<br> Of stevenaschroeder<br> Sent: Wednesday, January 07, 2009 11:24 AM<br> To: <a href="mailto:MPC500%40yahoogroups.com">MPC500@yahoogroups.<wbr>com</a><br> Subject: [MPC500] AN2789 - MPC5500 Configuration and Initialization<br> <br> I have been experimenting with Freescales, MPC5500 initialization code <br> and wonder if someone could clarify a few things for me. Running down <br> the list of configuration functions:<br> <br> cfg_CACHE - If I understand, the cache is not active out of reset, so <br> this simply enables it. (1) Why wouldn't you want to do this? (2) If <br> you know the particular part has cache, is there a need to check <br> L1CFG0?<br> <br> cfg_FMPLL - The Reference refers to setting the clock with your final <br> values with RFD+1, then reducing RFD after lock. (1) Why would you <br> want to set the clock to a series of rates, waiting for locks, such as <br> the 132MHz example? (2) What is the significance of inhibiting the <br> cache?<br> <br> cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably <br> bad--more than just loosing ECC, it may flip bits incorrectly on read?<br> <br> cfg_FLASH - What has changed at this point to allow less internal <br> flash wait states?<br> <br> cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any <br> reason to worry about this?<br> <br> Thanks in advance.<br> Steve<br> <br> [Non-text portions of this message have been removed]<br> <br> </p> </div> <!--~-|**|PrettyHtmlStart|**|-~--> <span width="1" style="color: white;">__._,_.___</span> <!-- Start the section with Message In topic --> <div id="ygrp-actbar"> <span class="left"> <a href="http://groups.yahoo.com/group/MPC500/message/3803;_ylc=X3oDMTM0ZzhsbzBqBF9TAzk3MzU5NzE0BGdycElkAzYyNzYzODcEZ3Jwc3BJZAMxNzA2NTU0MjA1BG1zZ0lkAzM5NzYEc2VjA2Z0cgRzbGsDdnRwYwRzdGltZQMxMjMxMzUwODU0BHRwY0lkAzM4MDM-"> Messages in this topic </a> (<span class="bld">5</span>) </span> <a href="http://groups.yahoo.com/group/MPC500/post;_ylc=X3oDMTJwdWh2M2ZjBF9TAzk3MzU5NzE0BGdycElkAzYyNzYzODcEZ3Jwc3BJZAMxNzA2NTU0MjA1BG1zZ0lkAzM5NzYEc2VjA2Z0cgRzbGsDcnBseQRzdGltZQMxMjMxMzUwODU0?act=reply&messageNum=3976"> <span class="bld"> Reply </span> (via web post) </a> | <a href="http://groups.yahoo.com/group/MPC500/post;_ylc=X3oDMTJlY3N0Mm05BF9TAzk3MzU5NzE0BGdycElkAzYyNzYzODcEZ3Jwc3BJZAMxNzA2NTU0MjA1BHNlYwNmdHIEc2xrA250cGMEc3RpbWUDMTIzMTM1MDg1NA--" class="bld"> Start a new topic </a> </div> <!------- Start Nav Bar ------> <!-- |**|begin egp html banner|**| --> <div id="ygrp-vitnav"> <a href="http://groups.yahoo.com/group/MPC500/messages;_ylc=X3oDMTJlbDV0bXM2BF9TAzk3MzU5NzE0BGdycElkAzYyNzYzODcEZ3Jwc3BJZAMxNzA2NTU0MjA1BHNlYwNmdHIEc2xrA21zZ3MEc3RpbWUDMTIzMTM1MDg1NA--">Messages</a> | <a href="http://groups.yahoo.com/group/MPC500/links;_ylc=X3oDMTJmbW1oczZmBF9TAzk3MzU5NzE0BGdycElkAzYyNzYzODcEZ3Jwc3BJZAMxNzA2NTU0MjA1BHNlYwNmdHIEc2xrA2xpbmtzBHN0aW1lAzEyMzEzNTA4NTQ-">Links</a> </div> <!-- |**|end egp html banner|**| --> <div id="ygrp-grft"> </div> <div id="ygrp-mkp"> <div id="hd">MARKETPLACE</div> <div id="ads"> <div class="ad"> <hr noshade="noshade" size="1"><a href="http://us.ard.yahoo.com/SIG=13rdcgi0m/M=493064.12016295.13271503.10835568/D=groups/S=1706554205:MKP1/Y=YAHOO/EXP=1231358054/L=/B=zfnfdkLaX.g-/J=1231350854667657/A=5530388/R=0/SIG=11nuutlas/*http://explore.yahoo.com/groups/kraftmealsmadesimple/">From kitchen basics to easy recipes - join the Group from Kraft Foods </a> </div> </div> </div> <!-- yahoo logo --> <!-- |**|begin egp html banner|**| --> <div id="ygrp-ft"> <a href="http://groups.yahoo.com/;_ylc=X3oDMTJkZm1ibTg2BF9TAzk3MzU5NzE0BGdycElkAzYyNzYzODcEZ3Jwc3BJZAMxNzA2NTU0MjA1BHNlYwNmdHIEc2xrA2dmcARzdGltZQMxMjMxMzUwODU0"> <img src="http://us.i1.yimg.com/us.yimg.com/i/yg/img/logo/ma_grp_160.gif" height="15" width="106" border="0" alt="Yahoo! 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