Re: Cycle Counting--Too Many

"Jake Grajewski [email protected] [msp430]" <[email protected]> Wed, 23 Sep 2015 13:59:02 -0700
Newsgroups gmane.comp.hardware.texas-instruments.msp430.discuss
Message-ID <CABROLXs==31wW4pc8jmYscLRPhOsyQ8Ry_wryVs3__wqa9W5_Q@mail.gmail.com>
See that's the problem you have the most notorious virus there is.....
Windows....

On Tue, Sep 22, 2015 at 11:00 AM, 'Redd, Emmett R'
[email protected] [msp430] <[email protected]> wrote:

>
>
> Please ignore today's previous email. Windows 10 and my touchpad sent it
> before I had put all the information contained in this email.
>
> Update: First a summary and then the details.
>
> Summary: There remain two extra cycles when going into and out of LPM3 and
> there is still one cycle short when the low-power bits are not cleared and
> the main never gets to run in active mode.
>
> Details:
>
> Since the xor and oscilloscope functions like a print statement for me in
> debugging, I decided to put one in between every operation I could. And,
> since the xor transitions on the falling edge of SMCLK, I will be counting
> the falling edge as the end of a cpu cycle.
>
> So, with the first instruction in the ISR being an xor, it should be 8
> (interrupt acceptance in LPM3) + 4 (xor) = 12 to first LED edge. That is
> what I count IF the long, SMCLK idling high, cycle is counted as the first
> cycle. Then comes the bic (5 cycles) to clear the low-power bits and xor (4
> cycles) for a total of 9. The next edge comes after the 5-cycle RETI and
> 4-cycle xor. The next edge comes after a 2-cycle jmp and a 4-cycle xor.
> Then comes the 2-cycle bis that sets the low-power bits and 2 unexplained
> cycles before the long cycle counted as the first cycle above.
>
> Speculation: Could it be that it takes an undocumented 2 cycles for the
> clocks to get into a low power mode like it takes a barely-documented 2
> cycles to get out?
>
> When not clearing the low-power bits in the ISR, the SMCLK burst remains 1
> cycle short. If RETI is the only instruction, 12 cycles (11 short and 1
> long) are all that appear. With the ISR consisting of two xors and RETI, it
> is 20 cycles long (19 short and 1 long). The first xor indicates that the
> long cycle remains with the 8 cycles of the interrupt acceptance in LPM3;
> the RETI is only 4 cycles (not 5 as documented).
>
> I cannot think of any experiments from here.
>
> Emmett Redd Ph.D. mailto:[email protected]
> Professor (417)836-5221
> Department of Physics, Astronomy, and Materials Science
> Missouri State University Fax (417)836-6226
> 901 SOUTH NATIONAL Lab (417)836-3770
> SPRINGFIELD, MO 65897 USA Dept (417)836-5131
>
> In statesmanship get the formalities right, never mind about the
> moralities. -- Mark Twain.
> ________________________________________
> From: [email protected] [[email protected]]
> Sent: Friday, September 18, 2015 3:16 PM
> To: MSP430 List
> Subject: Re: [msp430] Cycle Counting--Too Many
>
> On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
>
> > I think your argument in using only the figure on page 9-24
> > of SLAA024 is flawed in that the figure does not account for
> > Constant Generator use for the 6 (from memory?) constants
> > unless the reader makes the conversion to register mode for
> > them.
>
> I completely took your first post's point on this issue, as
> well. It makes sense, too. Just as you say. I take your point
> above, once again.
>
> > Now we could go back and forth on this for a long
> > time,
>
> I really didn't want to belabor things. I just wanted to
> tweek your thinking so that you'd do an experiment. The
> documentation wasn't outright explicit about it, as I read
> through it.
>
> > so I just programmed a second xor.b #0x1,&P1OUT to
> > immediately follow the first. The resulting pulse is 4
> > cycles long. And, just to be complete I changed the two
> > xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
>
> Perfect!
>
> ><snip>
> > Curiouser and curiouser: If I just comment out the clearing
> > of the low power modes within the ISR, I count a burst of 12
> > cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> > for RETI says the burst should be 13.
> ><snip>
>
> Interesting. I really enjoy seeing the detailed work going on
> here and will be very interested in how things resolve as you
> work through it. I do similar kinds of tests (often to the
> despair of those who would prefer I just accept "handwaving"
> and call it "close enough for horseshoes"), so I really like
> seeing when someone else is just as anal about the details as
> I prefer. Will be watching, so please do update when you have
> more information on this.
>
> Jon
>
> ------------------------------------
> Posted by: Jon Kirwan <[email protected]>
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>



-- 
Thomas J. Grajewski