CVS: msp430-libc/include/msp430 dma.h,1.3,1.4
Steve Underwood <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430-libc/include/msp430 In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv13544/msp430-libc/include/msp430 Modified Files: dma.h Log Message: Added missing DMA source/destination entries Index: dma.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/dma.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -w -d -r1.3 -r1.4 --- dma.h 28 Dec 2002 06:55:40 -0000 1.3 +++ dma.h 27 Sep 2005 16:16:12 -0000 1.4 @@ -72,6 +72,13 @@ #define DMA0TSEL_3 (3<<0) /* DMA channel 0 transfer select 3: I2C receive */ #define DMA0TSEL_4 (4<<0) /* DMA channel 0 transfer select 4: I2C transmit */ #define DMA0TSEL_5 (5<<0) /* DMA channel 0 transfer select 5: DAC12.0IFG */ +#define DMA0TSEL_6 (6<<0) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA0TSEL_7 (7<<0) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA0TSEL_8 (8<<0) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA0TSEL_9 (9<<0) /* DMA channel 0 transfer select 9: UART1 receive */ +#define DMA0TSEL_10 (10<<0) /* DMA channel 0 transfer select 10: UART1 transmit */ +#define DMA0TSEL_11 (11<<0) /* DMA channel 0 transfer select 11: Multiplier ready */ +#define DMA0TSEL_14 (14<<0) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */ #define DMA0TSEL_15 (15<<0) /* DMA channel 0 transfer select 15: DMAE0 */ #define DMA1TSEL_0 (0<<4) /* DMA channel 1 transfer select 0: DMA_REQ */ @@ -80,6 +87,13 @@ #define DMA1TSEL_3 (3<<4) /* DMA channel 1 transfer select 3: I2C receive */ #define DMA1TSEL_4 (4<<4) /* DMA channel 1 transfer select 4: I2C transmit */ #define DMA1TSEL_5 (5<<4) /* DMA channel 1 transfer select 5: DAC12.0IFG */ +#define DMA1TSEL_6 (6<<4) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA1TSEL_7 (7<<4) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA1TSEL_8 (8<<4) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA1TSEL_9 (9<<4) /* DMA channel 1 transfer select 9: UART1 receive */ +#define DMA1TSEL_10 (10<<4) /* DMA channel 1 transfer select 10: UART1 transmit */ +#define DMA1TSEL_11 (11<<4) /* DMA channel 1 transfer select 11: Multiplier ready */ +#define DMA1TSEL_14 (14<<4) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */ #define DMA1TSEL_15 (15<<4) /* DMA channel 1 transfer select 15: DMAE0 */ #define DMA2TSEL_0 (0<<8) /* DMA channel 2 transfer select 0: DMA_REQ */ @@ -88,6 +102,13 @@ #define DMA2TSEL_3 (3<<8) /* DMA channel 2 transfer select 3: I2C receive */ #define DMA2TSEL_4 (4<<8) /* DMA channel 2 transfer select 4: I2C transmit */ #define DMA2TSEL_5 (5<<8) /* DMA channel 2 transfer select 5: DAC12.0IFG */ +#define DMA2TSEL_6 (6<<8) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA2TSEL_7 (7<<8) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA2TSEL_8 (8<<8) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA2TSEL_9 (9<<8) /* DMA channel 2 transfer select 9: UART1 receive */ +#define DMA2TSEL_10 (10<<8) /* DMA channel 2 transfer select 10: UART1 transmit */ +#define DMA2TSEL_11 (11<<8) /* DMA channel 2 transfer select 11: Multiplier ready */ +#define DMA2TSEL_14 (14<<8) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */ #define DMA2TSEL_15 (15<<8) /* DMA channel 2 transfer select 15: DMAE0 */ #define ENNMI 0x0001 /* Enable NMI interruption of DMA */ ------------------------------------------------------- This SF.Net email is sponsored by: Power Architecture Resource Center: Free content, downloads, discussions, and more. http://solutions.newsforge.com/ibmarch.tmpl