CVS: jtag/funclets counterplus.S,NONE,1.1 counter.S,1.1,1.2 eraseFlash.S,1.4,1.5 eraseFlashSegment.S,1.1,1.2 makefile,1.7,1.8 progFlash.S,1.2,1.3
Chris Liechti <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/jtag/funclets
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv23202/jtag/funclets
Modified Files:
counter.S eraseFlash.S eraseFlashSegment.S makefile
progFlash.S
Added Files:
counterplus.S
Log Message:
- add counter funclet for F4xx devices (DCO+)
- the counter funclets accept DCO/DCO+ settings as parameter and they set up the clock controls
- change MCLK settings, now assume FCLK*5 ( was 2x before)
--- NEW FILE: counterplus.S ---
/* This implements a simple 32 bit up counter. It can be used to measure
the frequency of the DCO+ clock.
The funclet won't stop itself. The idea is that the host runs this funclet for
example for 100ms and then reads the registers R14:R15. The clock
frequency can then be aproximated:
f(dco) = (R14:R15*4)/(0.1s) [Hz]
Usage:
msp430-jtag --result=rall --timeout=0.1 --funclet counterplus.a43
This programm must be linked specialy so that it's placed in the RAM.
(see makefile).
The first six bytes and its contents are mandatory. Also must the funclet
end with a "jmp $" instruction.
chris <[email protected]>
*/
//~ #include <io.h>
#include <msp430x43x.h>
.text
start: .word start ; target address to download in MSP430
.word main ; staring address of code
.word stop ; end address, where the "jmp $" is located
scfi0: .byte 0
scfi1: .byte 14
scfqctl:.byte 0x80
fllctl0:.byte 0x80
fllctl1:.byte 0x00
.Ldummy:.byte 0
main: dint
bis.b #SCG0, r2 ; Disable FLL+.
mov.b scfqctl, &SCFQCTL ; init clock to given settings
mov.b scfi1, &SCFI1
mov.b fllctl0, &FLL_CTL0
mov.b fllctl1, &FLL_CTL1
mov.b scfi0, &SCFI0
clr R14
clr R15
.Lloop: inc R14 ; 1 ]
adc R15 ; 1 ]> 4 clocks/loop
jmp .Lloop ; 2 ]
nop ; PC points past the last instruction for
; a short time, ensure that it is not the
; stop address, and the funclet is stopped
; by accident
stop: jmp stop ; end of program, detected by library
Index: counter.S
===================================================================
RCS file: /cvsroot/mspgcc/jtag/funclets/counter.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -w -d -r1.1 -r1.2
--- counter.S 27 Dec 2005 01:12:11 -0000 1.1
+++ counter.S 27 Dec 2005 13:37:11 -0000 1.2
@@ -26,7 +26,13 @@
.word main ; staring address of code
.word stop ; end address, where the "jmp $" is located
-main: clr R14
+dco: .byte 3<<5
+bcs1: .byte 7
+
+main: dint
+ mov.b bcs1, &BCSCTL1 ; init clock to given settings
+ mov.b dco, &DCOCTL ; init clock to given settings
+ clr R14
clr R15
.Lloop: inc R14 ; 1 ]
Index: eraseFlash.S
===================================================================
RCS file: /cvsroot/mspgcc/jtag/funclets/eraseFlash.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -w -d -r1.4 -r1.5
--- eraseFlash.S 22 Dec 2005 01:49:34 -0000 1.4
+++ eraseFlash.S 27 Dec 2005 13:37:11 -0000 1.5
@@ -17,25 +17,24 @@
.word main
.word stop
-srinit: .word 0
-type: .word 0
-addr: .word 0
+srinit: .word 0 ; arg 1
+type: .word 0 ; arg 2
+addr: .word 0 ; arg 3
main: mov #WDTPW|WDTHOLD, &WDTCTL ;Disable Watchdog.
dint ;Disable interrupts.
mov srinit, r2 ;Initialize status register (Possibly disable FLL+).
-; mov #0xa544, &FCTL2 ;Source = MCLK, DIV = 5.
- mov #0xa541, &FCTL2 ;Source = MCLK, DIV = 2.
- mov #0xa500, &FCTL3 ;Clear bits.
+ mov #FWKEY|44, &FCTL2 ; Source = MCLK, DIV = 5.
+ mov #FWKEY, &FCTL3 ; Clear bits.
mov #19, r9 ;Bug requires additional erase cycles.
.LAgain:mov type, &FCTL1 ;Load FCTL1 value. MUST CONTAIN PASSWORD.
mov addr, r10 ;Load (page) address to erase.
mov #0xffff, 0(r10) ;Write data into the address (to erase the FLASH).
- mov #5300/3+1, r10 ;Delay for FLASH to erase (BUSY does not work on older devices).
+ mov #(2*5300/3)+1, r10 ; Delay for FLASH to erase (BUSY does not work on older devices).
.LWait: dec r10 ;Loop requires 3 clock cycles.
jnz .LWait ;
- mov #0xA500, &FCTL1 ;Clear ERASE + MERAS bits.
- mov #0xA500, &FCTL3 ;Clear BUSY + LOCK bits.
+ mov #FWKEY, &FCTL1 ; Clear ERASE + MERAS bits.
+ mov #FWKEY, &FCTL3 ; Clear BUSY + LOCK bits.
dec r9 ;Loop on erase cycles.
jnz .LAgain ;
Index: eraseFlashSegment.S
===================================================================
RCS file: /cvsroot/mspgcc/jtag/funclets/eraseFlashSegment.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -w -d -r1.1 -r1.2
--- eraseFlashSegment.S 22 Dec 2005 20:03:23 -0000 1.1
+++ eraseFlashSegment.S 27 Dec 2005 13:37:11 -0000 1.2
@@ -19,15 +19,14 @@
.word main
.word stop
-srinit: .word 0
-type: .word 0
-addr: .word 0
+srinit: .word 0 ; arg 1
+type: .word 0 ; arg 2
+addr: .word 0 ; arg 3
main: mov #WDTPW|WDTHOLD, &WDTCTL ;Disable Watchdog.
dint ;Disable interrupts.
mov srinit, r2 ;Initialize status register (Possibly disable FLL+).
-; mov #0xa544, &FCTL2 ;Source = MCLK, DIV = 5.
- mov #FWKEY|0x41, &FCTL2 ;Source = MCLK, DIV = 2.
+ mov #FWKEY|44, &FCTL2 ; Source = MCLK, DIV = 5.
mov #FWKEY, &FCTL3 ;Clear bits.
mov #1, r9 ;just one loop suffices for segment erase
@@ -44,7 +43,7 @@
.LAgain:mov type, &FCTL1 ;Load FCTL1 value. MUST CONTAIN PASSWORD.
mov addr, r10 ;Load (page) address to erase.
mov #0xffff, 0(r10) ;Write data into the address (to erase the FLASH).
- mov #4820/3+1, r10 ;Delay for FLASH to erase (BUSY does not work on older devices).
+ mov #(2*4820)/3+1, r10 ; Delay for FLASH to erase (BUSY does not work on older devices).
.LWait: dec r10 ;Loop requires 3 clock cycles.
jnz .LWait ;
mov #FWKEY, &FCTL1 ;Clear ERASE + MERAS bits.
Index: makefile
===================================================================
RCS file: /cvsroot/mspgcc/jtag/funclets/makefile,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -w -d -r1.7 -r1.8
--- makefile 27 Dec 2005 01:12:11 -0000 1.7
+++ makefile 27 Dec 2005 13:37:11 -0000 1.8
@@ -19,6 +19,7 @@
progFlash.ci progFlash.lst \
ramsizeDetect.ci ramsizeDetect.lst \
counter.ci counter.lst \
+ counterplus.ci counterplus.lst \
#~ regtest.a43 blinking.a43
#pattern rule for funclets
@@ -34,7 +35,7 @@
#general rule to make a listing elf->lst
%.lst: %.elf
- msp430-objdump >$@ -DS $<
+ msp430-objdump >$@ -dS $<
#convert intel hex/a43 files to includable C files
%.ci: %.a43
Index: progFlash.S
===================================================================
RCS file: /cvsroot/mspgcc/jtag/funclets/progFlash.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -w -d -r1.2 -r1.3
--- progFlash.S 8 Jan 2003 04:44:35 -0000 1.2
+++ progFlash.S 27 Dec 2005 13:37:11 -0000 1.3
@@ -22,20 +22,19 @@
dint ;Disable interrupts.
mov srinit, r2 ;Initialize status register (Possibly disable FLL+).
mov #0xffff, &CCR0 ;CCR is used as return value -> error
-; mov #0xa544, &FCTL2 ;Source = MCLK, DIV = 5.
- mov #0xa541, &FCTL2 ;Source = MCLK, DIV = 2
- mov #0xa500, &FCTL3 ;Clear bits.
+ mov #FWKEY|44, &FCTL2 ; Source = MCLK, DIV = 5.
+ mov #FWKEY, &FCTL3 ; Clear bits.
mov addr, r9 ;Address to program.
mov length, r8 ;Length to program.
mov #buffer, r10 ;Buffer to program.
.LProg: cmp @R10, 0(r9) ;Value already present?
jeq .LNext ;Yes, so skip and advance to next.
- mov #(0xa500|WRT), &FCTL1 ;No, so enable writing to flash.
+ mov #FWKEY|WRT, &FCTL1 ; No, so enable writing to flash.
mov @R10, 0(r9) ;Write data to flash.
.LWait: bit #BUSY, &FCTL3 ;Wait for completion of write.
jnz .LWait ;Busy bit is cleared upon completion.
- mov #0xa500, &FCTL1 ;Reset writing to flash.
- mov #0xa500, &FCTL3 ;Clear BUSY + LOCK bits.
+ mov #FWKEY, &FCTL1 ; Reset writing to flash.
+ mov #FWKEY, &FCTL3 ; Clear BUSY + LOCK bits.
cmp @R10, 0(r9) ;Verify written data.
jne stop ;Verification failure
.LNext: incd r10 ;Advance source pointer.
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