CVS: libraries/include/mspgcc fll.h,1.2,1.3

Update of /cvsroot/mspgcc/libraries/include/mspgcc
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv26600/libraries/include/mspgcc

Modified Files:
	fll.h 
Log Message:
the FLL actualy sets up SMCLK not MCLK (which makes a difference if a divider is selected on SMCLK)

Index: fll.h
===================================================================
RCS file: /cvsroot/mspgcc/libraries/include/mspgcc/fll.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -w -d -r1.2 -r1.3
--- fll.h	29 Sep 2005 19:07:11 -0000	1.2
+++ fll.h	27 Dec 2005 22:53:48 -0000	1.3
@@ -2,16 +2,16 @@
 #define MSPGCC_FLL_H
 
 /**
- * Formula to calculate the multiplier, for fll_adjust(), based on MCLK
+ * Formula to calculate the multiplier, for fll_adjust(), based on SMCLK
  * and ACLK.
  *
- * @param mclk  the desired MCLK speed (after divider)
+ * @param mclk  the desired SMCLK speed (after divider)
  * @param aclk  the actual ACLK speed (after divider)
  */
-#define FLL_MULTIPLIER(mclk, aclk)   ((mclk)/(aclk))
+#define FLL_MULTIPLIER(smclk, aclk)   ((smclk)/(aclk))
 
 /**
- * Adjust MCLK using ACLK, doing the software FLL in 1xx devices.
+ * Adjust SMCLK using ACLK, doing the software FLL in F1xx devices.
  *
  * This function modifies TACTL, CCR2, CCTL2, BCSCTL1 and DCOCTL.
  * The Timer_A module has to be re-setup by the user after this function



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