CVS: msp430simu core.py,1.15,1.16 simugui.py,1.11,1.12 testing.h,1.3,1.4 testing.py,1.4,1.5 testing_example.c,1.4,1.5
Chris Liechti <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430simu
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv32477/msp430simu
Modified Files:
core.py simugui.py testing.h testing.py testing_example.c
Log Message:
- several fixes
- logging system and messages updated
- test message output API changed
Index: core.py
===================================================================
RCS file: /cvsroot/mspgcc/msp430simu/core.py,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -w -d -r1.15 -r1.16
--- core.py 12 Aug 2005 21:18:56 -0000 1.15
+++ core.py 29 Dec 2005 21:17:23 -0000 1.16
@@ -37,8 +37,8 @@
# watches log access on specific addresses in memory
class AddressWatch:
- def __init__(self, log, description):
- self.log = log
+ def __init__(self, description):
+ self.log = logging.getLogger('watch')
self.description = description
def __call__(self, address, bytemode, oldvalue, newvalue):
@@ -58,8 +58,8 @@
))
class MemoryAccessWatch:
- def __init__(self, log, condition_fu, description):
- self.log = log
+ def __init__(self, condition_fu, description):
+ self.log = logging.getLogger('watch')
self.description = description
self.condition_fu = condition_fu
@@ -75,23 +75,24 @@
class Register(Subject):
"""generic register"""
- def __init__(self, core, reg=0, regnum=None, log=None):
+ def __init__(self, core, reg=0, regnum=None):
Subject.__init__(self) #init model for observer pattern
self.core = core
self.reg = reg
self.regnum = regnum
- self.log = log
+ self.log = logging.getLogger('register')
+ self.log.debug('initiliaize R%02d -> 0x%04x' % (self.regnum, reg))
def set(self, value, bytemode=0, am=0):
"""write value to register"""
- if self.log: self.log.info('REGSTR: write 0x%04x -> R%02d mode:%s\n' % (value, self.regnum, bytemode and 'b' or 'w'))
+ self.log.debug('write 0x%04x -> R%02d mode:%s' % (value, self.regnum, bytemode and 'b' or 'w'))
self.reg = value & (bytemode and 0xff or 0xffff)
self.notify()
def get(self, bytemode=0, am=0):
"""read register"""
value = self.reg & (bytemode and 0xff or 0xffff)
- if self.log: self.log.info('REGSTR: read R%02d -> 0x%04x mode:%s\n' % (self.regnum, value, bytemode and 'b' or 'w'))
+ self.log.debug('read R%02d -> 0x%04x mode:%s' % (self.regnum, value, bytemode and 'b' or 'w'))
return value
def __getitem__(self,index):
@@ -113,10 +114,14 @@
#programm counter
class PC(Register):
"""Program counter"""
+
+ def __init__(self, core, reg=0):
+ Register.__init__(self, core, reg=reg, regnum=0)
+
def next(self):
value = self.core.memory.get(bytemode=0, address=self.reg)
self.set( self.get() + 2)
- if self.log: self.log.info('REGSTR: next @PC, PC+\n')
+ if self.log: self.log.debug('next @PC, PC+')
return value
def __repr__(self):
@@ -129,16 +134,20 @@
class SP(Register):
"""Stack pointer"""
+
+ def __init__(self, core, reg=0):
+ Register.__init__(self, core, reg=reg, regnum=1)
+
def push(self,value):
self.reg -= 2
- if self.log: self.log.info('REGSTR: push @-SP, 0x%04x\n' % (value))
+ if self.log: self.log.debug('push @-SP, 0x%04x' % (value))
self.core.memory.set(bytemode=0, address=self.reg, value=value)
self.notify()
def pop(self):
value = self.core.memory.get(bytemode=0, address=self.reg)
self.reg += 2
- if self.log: self.log.info('REGSTR: pop @SP+ 0x%04x\n' % (value))
+ if self.log: self.log.debug('pop @SP+ -> 0x%04x' % (value))
self.notify()
return value
@@ -154,6 +163,9 @@
"""SR combined with Constant Generator Register 1"""
consts = (None,None,4,8)
+ def __init__(self, core, reg=0):
+ Register.__init__(self, core, reg=reg, regnum=2)
+
bits = {
'C': 0x0001,
'Z': 0x0002,
@@ -188,7 +200,7 @@
def get(self, bytemode=0, am=0):
if am == 0: return self.reg & (bytemode and 0xff or 0xffff)
value = self.consts[am] & (bytemode and 0xff or 0xffff)
- if self.log: self.log.info('REGSTR: read R%02d -> 0x%04x mode:%s\n' % (self.regnum, value, bytemode and 'b' or 'w'))
+ if self.log: self.log.debug('REGSTR: read R%02d -> 0x%04x mode:%s' % (self.regnum, value, bytemode and 'b' or 'w'))
return value
def __repr__(self):
@@ -207,9 +219,12 @@
"""Constant Generator Register 2"""
consts = (0,1,2,0xffff)
+ def __init__(self, core, reg=0):
+ Register.__init__(self, core, reg=reg, regnum=3)
+
def get(self, bytemode=0, am=0):
value = self.consts[am] & (bytemode and 0xff or 0xffff)
- if self.log: self.log.info('REGSTR: read R%02d -> 0x%04x mode:%s\n' % (self.regnum, value, bytemode and 'b' or 'w'))
+ if self.log: self.log.debug('read R%02d -> 0x%04x mode:%s' % (self.regnum, value, bytemode and 'b' or 'w'))
return value
def __repr__(self):
@@ -223,8 +238,8 @@
##################################################################
class Peripheral:
color = (0x33, 0x33, 0x33) #color for graphical representation
- def __init__(self, log):
- self.log = log
+ def __init__(self):
+ self.log = logging.getLogger('peripheral')
self.reset() #init device
def __contains__(self, address):
@@ -247,10 +262,11 @@
"""flash memory"""
color = (0xff, 0xaa, 0x88) #color for graphical representation
- def __init__(self, log, startaddress = 0xf000, endaddress = 0xffff):
+ def __init__(self, startaddress = 0xf000, endaddress = 0xffff):
self.startaddress = startaddress
self.endaddress = endaddress
- Peripheral.__init__(self, log) #calls self.reset()
+ Peripheral.__init__(self) #calls self.reset()
+ self.log = logging.getLogger('flash')
def __contains__(self, address):
"""return true if address is handled by this peripheral"""
@@ -282,10 +298,11 @@
"""RAM memory"""
color = (0xaa, 0xff, 0x88) #color for graphical representation
- def __init__(self, log, startaddress = 0x0200, endaddress = 0x02ff):
+ def __init__(self, startaddress = 0x0200, endaddress = 0x02ff):
self.startaddress = startaddress
self.endaddress = endaddress
- Peripheral.__init__(self, log) #calls self.reset()
+ Peripheral.__init__(self) #calls self.reset()
+ self.log = logging.getLogger('RAM')
def __contains__(self, address):
"""return true if address is handled by this peripheral"""
@@ -437,22 +454,22 @@
def set(self, address, value, bytemode=0):
"""write value to address"""
if not bytemode and self.log:
- self.log.info('PERIPH: Access Error - expected byte but got word access\n')
+ self.log.error('PERIPH: Access Error - expected byte but got word access')
self.values[address] = value & 0xff
def get(self, address, bytemode=0):
"""read from address"""
if not bytemode and self.log:
- self.log.info('PERIPH: Access Error - expected byte but got word access\n')
+ self.log.error('PERIPH: Access Error - expected byte but got word access')
return self.values[address]
class Memory(Subject):
# color = (0xaa, 0xaa, 0xaa) #color for graphical representation
color = (0xff, 0xff, 0xff) #color for graphical representation
- def __init__(self, log=None):
+ def __init__(self):
Subject.__init__(self) #init model for observer pattern
- self.log = log
+ self.log = logging.getLogger('memory')
self.setwatches = {} #serached on reads
self.getwatches = {} #serached on writes
self.accesswatches = [] #searched allways
@@ -475,8 +492,8 @@
self.notify()
def load(self, filename):
- "fill memory with the contents of a file. file type is determined from extension"
- self.log.info('MEMORY: loading file %s\n' % filename)
+ """fill memory with the contents of a file. file type is determined from extension"""
+ self.log.info('loading file %s' % filename)
if filename[-4:].lower() == '.txt':
self.loadTIText(open(filename, "r"))
else:
@@ -486,7 +503,7 @@
"""load data from a (opened) file in Intel-HEX format"""
for l in file.readlines():
if l[0] != ':':
- raise "file format error"
+ raise IOError("file format error")
l = l.strip() #fix CR-LF issues...
count = int(l[1:3],16)
address = int(l[3:7],16)
@@ -540,7 +557,7 @@
def set(self, address, value, bytemode=0):
"""write value to address"""
- self.log.info('MEMORY: write 0x%04x <- 0x%04x mode:%s' % (address, value, bytemode and 'b' or 'w'))
+ self.log.debug('write 0x%04x <- 0x%04x mode:%s' % (address, value, bytemode and 'b' or 'w'))
if self.setwatches.has_key(address): self.setwatches[address](address, bytemode, self.memory[address], value) #call watch
for a in self.accesswatches: a(self, bytemode, 1, address)
self._set(address, value, bytemode)
@@ -564,7 +581,7 @@
if self.getwatches.has_key(address): self.getwatches[address](address, bytemode, self.memory[address], None) #call watch
for a in self.accesswatches: a(self, bytemode, 0, address)
value = self._get(address, bytemode)
- self.log.info('MEMORY: read 0x%04x -> 0x%04x mode:%s' % (address, value, bytemode and 'b' or 'w'))
+ self.log.debug('read 0x%04x -> 0x%04x mode:%s' % (address, value, bytemode and 'b' or 'w'))
return value
def hexline(self, address, width=16):
@@ -584,7 +601,7 @@
while (toadr is not None and adr < toadr+1) or (toadr is None) and len(res) < lines:
res.append('%s %s %s' % (self.hexline(adr)))
adr += 16
- return res
+ return '\n'.join(res)
##################################################################
## argument wrappers
@@ -1026,28 +1043,28 @@
# methods
#------------------------
- def __init__(self, log=None):
+ def __init__(self):
"""initialize core with registers and memory"""
Subject.__init__(self) #init model for observer pattern
- self.log = log #logging.getLogger('msp430 core')
- self.memory = Memory(log)
+ self.log = logging.getLogger('core')
+ self.memory = Memory()
self.R = (
- PC(self, regnum=0, log=log),
- SP(self, regnum=1, log=log),
- SR(self, regnum=2, log=log),
- CG2(self, regnum=3, log=log),
- Register(self, regnum=4, log=log),
- Register(self, regnum=5, log=log),
- Register(self, regnum=6, log=log),
- Register(self, regnum=7, log=log),
- Register(self, regnum=8, log=log),
- Register(self, regnum=9, log=log),
- Register(self, regnum=10, log=log),
- Register(self, regnum=11, log=log),
- Register(self, regnum=12, log=log),
- Register(self, regnum=13, log=log),
- Register(self, regnum=14, log=log),
- Register(self, regnum=15, log=log)
+ PC(self),
+ SP(self),
+ SR(self),
+ CG2(self),
+ Register(self, regnum=4),
+ Register(self, regnum=5),
+ Register(self, regnum=6),
+ Register(self, regnum=7),
+ Register(self, regnum=8),
+ Register(self, regnum=9),
+ Register(self, regnum=10),
+ Register(self, regnum=11),
+ Register(self, regnum=12),
+ Register(self, regnum=13),
+ Register(self, regnum=14),
+ Register(self, regnum=15)
)
#alisses
self.PC = self.R[0]
@@ -1124,7 +1141,7 @@
', '.join(map(str,args[1:])),
cycles
)
- self.log.info('step: %s' % (note))
+ self.log.debug('step: %s' % (note,))
if execfu:
apply(execfu, [self]+args)
else:
@@ -1140,18 +1157,18 @@
##################################################################
class Tracer:
- def __init__(self, core, log):
+ def __init__(self, core):
self.core = core
- self.log = log
+ self.log = logging.getLogger('trace')
def start(self, startadr, maxsteps=100):
- self.log.info( 'TRACER: set startaddress\n')
+ self.log.info('set startaddress')
self.core.PC.set(startadr)
- self.log.info( 'TRACER: *** starting trace (maxsteps=%d)\n' % (maxsteps))
+ self.log.info('*** starting trace (maxsteps=%d)' % (maxsteps))
step = 1
while step <= maxsteps:
self.core.step()
- self.log.info( 'TRACER: (step %d, cycle %d)\n%r\n' % (
+ self.log.info('step %d, cycle %d\n%r' % (
step, self.core.cycles, self.core))
step += 1
@@ -1160,16 +1177,16 @@
##################################################################
if __name__ == '__main__':
- logging.basicConfig()
+ logging.basicConfig(level=logging.DEBUG)
log = logging.getLogger('trace')
- core = Core(log)
+ core = Core()
core.SR.Z = 243
print core.SR.Z
print repr(core.SR)
#~ core.memory.load('tests.a43')
- #~ core.memory.load('../exmaples/leds/leds.a43')
+ core.memory.load('../examples/leds/leds.a43')
#~ print "-"*40, "memory dump"
#~ print '\n'.join(core.memory.hexdump(0xF000, 0xF086))
@@ -1186,10 +1203,9 @@
## print repr(core)
print "-"*40, "trace"
- core.memory.getwatches[0x200] = AddressWatch(log, "Variable one READ")
- core.memory.setwatches[0x200] = AddressWatch(log, "Variable one WRITE")
+ core.memory.getwatches[0x200] = AddressWatch("Variable one READ")
+ core.memory.setwatches[0x200] = AddressWatch("Variable one WRITE")
core.memory.accesswatches.append(MemoryAccessWatch(
- log,
lambda mem, wrt, adr: not( #F1121 layout
0x0000 <= adr <= 0x01ff or #Peripherals (not detailed)
0x0200 <= adr <= 0x02ff or #RAM
@@ -1199,17 +1215,17 @@
'Illegal memory access',
))
core.memory.accesswatches.append(MemoryAccessWatch(
- log,
lambda mem, wrt, adr: wrt and( #F1121 layout
0x1000 <= adr <= 0x10ff or #INFOMEM
0xf000 <= adr <= 0xffff #FLASH
),
'flash memory written',
))
- core.memory.hexdump(0x0200, 0x02ff, log)
- tracer = Tracer(core, log)
+ print core.memory.hexdump(0x0200, 0x02ff, log)
+ tracer = Tracer(core)
tracer.start(0xf000, 43) #only N steps
- core.memory.hexdump(0x0200, 0x02ff, log)
+ print "-"*40, "end"
+ print core.memory.hexdump(0x0200, 0x02ff, log)
Index: simugui.py
===================================================================
RCS file: /cvsroot/mspgcc/msp430simu/simugui.py,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -w -d -r1.11 -r1.12
--- simugui.py 14 Apr 2002 22:40:38 -0000 1.11
+++ simugui.py 29 Dec 2005 21:17:23 -0000 1.12
@@ -7,7 +7,7 @@
import core
##################################################################
-## view for disassebled memory
+## view for disassembled memory
##################################################################
class DisTable(wxPyGridTableBase):
"""Data model for wxGrid """
@@ -56,7 +56,7 @@
pass
return self.attr1.Clone()
- def disasseble(self, address, lines = 0):
+ def disassemble(self, address, lines = 0):
#if not self.core: return
self.discache = []
linelist = []
@@ -103,8 +103,8 @@
self.table.core = self.core = core
#update display
- def disasseble(self, address, lines = 0):
- self.table.disasseble(address, lines)
+ def disassemble(self, address, lines = 0):
+ self.table.disassemble(address, lines)
self.Refresh()
@@ -134,11 +134,11 @@
def GetValue(self, row, col):
if self.core:
if col==0:
- return "0x%04x" % (row * 0xf)
+ return "0x%04x" % (row * 16)
elif col == 17: #ASCII view
address = row<<4
bytes = [self.core.memory._get(a, bytemode=1) for a in range(address, address+16)]
- return ('%c'*len(bytes)) % tuple(map(lambda x: x>32 and x or ord('.'), bytes)) #ascii
+ return ('%c'*len(bytes)) % tuple(map(lambda x: 32<=x<127 and x or ord('.'), bytes)) #ascii
else:
return "%02x" % self.core.memory._get( (row<<4) + col, bytemode=1)
#return self.core.memory.hexline(row<<4)[col] #very inefficient here!
@@ -397,7 +397,7 @@
address = int(s,16)
else:
address = int(s)
- self.dis.disasseble(address)
+ self.dis.disassemble(address)
#self.mem.EnsureVisible(address/16)
def OnSizeWindow(self, event=None):
@@ -485,11 +485,11 @@
#create cpu core
##TODO: isolate this ##$$$$$$$
- self.core = core.Core(self)
- self.core.memory.append(core.ExtendedPorts(self.log))
- self.core.memory.append(core.Flash(self.log))
- self.core.memory.append(core.RAM(self.log))
- self.core.memory.append(core.Multiplier(self.log))
+ self.core = core.Core()
+ self.core.memory.append(core.ExtendedPorts())
+ self.core.memory.append(core.Flash())
+ self.core.memory.append(core.RAM())
+ self.core.memory.append(core.Multiplier())
self.core.attach(self) #register as observer
self.dis.SetCore(self.core)
@@ -521,7 +521,7 @@
self.lastpath = '.'
#self.update() #init displays
#self.OnScrollMem() #init scollbar
- #self.disasseble(0)
+ #self.disassemble(0)
#observer pattern
def update(self, *args):
@@ -531,7 +531,7 @@
for r in self.core.R:
regs += '%r\n' % r
self.registers.SetValue(regs)
- self.dis.disasseble(self.core.PC.get(), lines = 20) #update lockahead
+ self.dis.disassemble(self.core.PC.get(), lines = 20) #update lookahead
#update text in statusbar
self.SetStatusText('%r' % (args,), 0)
self.log.SetValue(''.join(self.loglines))
@@ -551,9 +551,10 @@
def OnMenuOpen(self, event=None):
dlg = wxFileDialog(self,
- "Choose a ihex file",
+ "Choose a MSP430 binary file",
".",
"",
+ #~ "MSP430 ELF(*.elf)|*.elf|Intel HEX (*.a43)|*.a43|TI Text(*.txt)|*.txt",
"Intel HEX (*.a43)|*.a43|TI Text(*.txt)|*.txt",
wxOPEN
)
@@ -561,7 +562,7 @@
if dlg.ShowModal() == wxID_OK:
self.lastpath = dlg.GetDirectory()
self.core.memory.load(dlg.GetPath())
- self.core.PC.set(self.core.memory.get(0xfffe)) ##DEBUG !!!!!!!!!!!
+ self.core.PC.set(self.core.memory.get(0xfffe)) #XXX DEBUG !!!!!!!!!!!
self.update()
dlg.Destroy()
@@ -617,6 +618,9 @@
#application....
if __name__ == '__main__':
+ #~ import logging
+ #~ logging.basicConfig(level=logging.DEBUG)
+
# Every wxWindows application must have a class derived from wxApp
class MyApp(wxApp):
# wxWindows calls this method to initialize the application
Index: testing.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430simu/testing.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -w -d -r1.3 -r1.4
--- testing.h 13 Mar 2002 23:50:07 -0000 1.3
+++ testing.h 29 Dec 2005 21:17:23 -0000 1.4
@@ -19,6 +19,8 @@
#define SUBTEST_START 0x20 //A new subtest begins
#define SUBTEST_SUCCESS 0x21 //The subtest was successful
#define SUBTEST_FAIL 0x22 //The subtest has failed
+#define SUBTEST_EXECUTE 0x2e //subtest is running
+#define SUBTEST_EXECUTE_DONE 0x2f //subtest is finished
//use the following macros in your test programms
@@ -32,9 +34,9 @@
#define END_TEST TEST_CMD = TEST_END
//not realy useful ones, look below
-#define SUBTEST(desc) TEST_CMD = SUBTEST_START, test_puts(desc)
-#define FAIL(desc) TEST_CMD = SUBTEST_FAIL, test_puts(desc)
-#define SUCCESS(desc) TEST_CMD = SUBTEST_SUCCESS, test_puts(desc)
+#define SUBTEST(desc) test_puts(desc), TEST_CMD = SUBTEST_START, TEST_CMD = SUBTEST_EXECUTE
+#define FAIL(desc) TEST_CMD = SUBTEST_EXECUTE_DONE, test_puts(desc), TEST_CMD = SUBTEST_FAIL
+#define SUCCESS(desc) TEST_CMD = SUBTEST_EXECUTE_DONE, test_puts(desc), TEST_CMD = SUBTEST_SUCCESS
#define OK SUCCESS
//use this for the subtests: e.g. 'CHECK("is a==b?", a==b)'
@@ -42,7 +44,7 @@
//not so nice to put C code in a h...
//but it saves linking separate sources for mostly simple tests files.
-void test_puts(char * text) {
+static void test_puts(char * text) {
while (*text) TEST_TEXTOUT = *text++;
}
Index: testing.py
===================================================================
RCS file: /cvsroot/mspgcc/msp430simu/testing.py,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -w -d -r1.4 -r1.5
--- testing.py 15 Mar 2002 02:16:38 -0000 1.4
+++ testing.py 29 Dec 2005 21:17:23 -0000 1.5
@@ -16,7 +16,7 @@
#please look at the example_tests.c and testing.h for more details on
#how to write tests
-import sys, core
+import sys, core, logging
#CMD codes:
IDLE = 0x00
@@ -25,16 +25,20 @@
SUBTEST_START = 0x20
SUBTEST_SUCCESS = 0x21
SUBTEST_FAIL = 0x22
+SUBTEST_EXECUTE = 0x2e
+SUBTEST_EXECUTE_DONE = 0x2f
class Testing(core.Peripheral):
color = (0x66, 0xff, 0xee) #color for graphical representation
def __init__(self, log, startaddress = 0x01b0):
self.startaddress = startaddress
- core.Peripheral.__init__(self, log) #calls self.reset()
+ core.Peripheral.__init__(self) #calls self.reset()
+ self.log = logging.getLogger('test io')
self.mode = IDLE
self.testcount = 0
self.failures = 0
+ self.text_buffer = []
def __contains__(self, address):
"""return true if address is handled by this peripheral"""
@@ -47,27 +51,40 @@
def set(self, address, value, bytemode=0):
"""read from address"""
if not bytemode and self.log:
- self.log.write('TESTNG: Access Error - expected byte but got word access\n')
+ self.log.error('TESTNG: Access Error - expected byte but got word access')
a = address - self.startaddress
if a == 0: #CMD
if value == TEST_START:
- sys.stdout.write("***************************\n")
+ self.log.info("Test start")
+ elif value == TEST_END:
+ self.log.info("Test finished")
elif value == SUBTEST_START:
self.testcount += 1
- sys.stdout.write("-----------------\n")
+ self.log.info("Test: %r" % ''.join(self.text_buffer))
+ del self.text_buffer[:]
elif value == SUBTEST_SUCCESS:
- sys.stdout.write("SUCCESS\n")
+ self.log.info("SUCCESS: %r" % ''.join(self.text_buffer))
+ del self.text_buffer[:]
elif value == SUBTEST_FAIL:
- sys.stdout.write("FAIL\n")
+ self.log.error("FAIL: %r" % ''.join(self.text_buffer))
+ del self.text_buffer[:]
self.failures += 1
+ elif value == SUBTEST_EXECUTE:
+ del self.text_buffer[:]
+ elif value == SUBTEST_EXECUTE_DONE:
+ if self.text_buffer:
+ self.log.info(''.join(self.text_buffer))
+ del self.text_buffer[:]
+ else:
+ self.log.error('unknown value 0x%02x written to test port' % value)
self.mode = value
elif a == 1: #TEXT OUT
- sys.stdout.write(chr(value))
+ self.text_buffer.append(chr(value))
def get(self, address, bytemode=0):
"""write value to address"""
if not bytemode and self.log:
- self.log.write('TESTNG: Access Error - expected byte but got word access\n')
+ self.log.error('TESTNG: Access Error - expected byte but got word access')
return 0 #no functionality right now
class TestCore(core.Core):
@@ -75,18 +92,18 @@
core.Core.__init__(self, log)
self.testing = Testing(log)
self.memory.append(self.testing) #insert new peripherals in MSP's address pace
- self.memory.append(core.Multiplier(self.log))
+ self.memory.append(core.Multiplier())
#self.reset()
def start(self, maxsteps=2000):
- self.log.write( 'TSTCOR: set startaddress\n')
+ self.log.debug( 'TSTCOR: set startaddress')
self.PC.set(self.memory.get(0xfffe))
- self.log.write( 'TSTCOR: *** starting trace (maxsteps=%d)\n' % (maxsteps))
+ self.log.debug( 'TSTCOR: *** starting trace (maxsteps=%d)' % (maxsteps))
step = 1
forever = 0
while forever or step <= maxsteps:
self.step()
- self.log.write( 'TSTCOR: (step %d, cycle %d)\n%r\n' % (
+ self.log.debug( 'TSTCOR: (step %d, cycle %d)\n%r' % (
step, self.cycles, self))
step += 1
if self.testing.mode == TEST_END:
@@ -97,11 +114,16 @@
print "This is not a file for the tester!"
if __name__ == '__main__':
- log = open("testing.log","w")
+ logging.basicConfig(level=logging.INFO,
+ format='%(asctime)s %(levelname)s %(message)s',
+ filename='testing.log',
+ filemode='w')
+ log = logging.getLogger('testing')
+
failures = 0
for f in sys.argv[1:]:
print "Running Test: %s ...\n" % f
- log.write("Running Test: %s ...\n" % f)
+ log.info("Running Test: %s ..." % f)
msp = TestCore(log)
msp.memory.load(f)
msp.start()
Index: testing_example.c
===================================================================
RCS file: /cvsroot/mspgcc/msp430simu/testing_example.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -w -d -r1.4 -r1.5
--- testing_example.c 13 Mar 2002 23:50:10 -0000 1.4
+++ testing_example.c 29 Dec 2005 21:17:23 -0000 1.5
@@ -27,170 +27,170 @@
unsigned long ulx, uly;
void subt1(void) {
- SUBTEST("Example Subtest\n"); //Begin with a new test
+ SUBTEST("Example Subtest"); //Begin with a new test
//set up test inputs
a = '0';
b = 'A';
//perform the calculation to be tested
r = (a << 8) | b;
- CHECK("leftshift:\t", r == 0x3041);
+ CHECK("leftshift", r == 0x3041);
}
void booltest(void) {
static char st = 0;
- SUBTEST("boolean not\n"); //Begin with a new test
+ SUBTEST("boolean not"); //Begin with a new test
//set up test inputs
//perform the calculation to be tested
st = 0;
st = !st;
st = !st;
r = 1;
- CHECK("st == !!st:\t", st == !!st );
- CHECK("st == 0:\t", st == 0 );
- CHECK("r == 1:\t", r == 1 );
- CHECK("r is true?:\t", r);
- CHECK("!r == 0:\t", !r == 0);
+ CHECK("st == !!st", st == !!st );
+ CHECK("st == 0", st == 0 );
+ CHECK("r == 1", r == 1 );
+ CHECK("r is true?", r);
+ CHECK("!r == 0", !r == 0);
}
void slongmul(void) {
- SUBTEST("signed long multiplication\n"); //Begin with a new test
- lx = -1L; ly = 0x1000L; CHECK("-1*0x1000:\t", (lx*ly) == -0x1000L );
- lx = -10L; ly = 0x1000L; CHECK("-10*0x1000:\t", (lx*ly) == -(10*0x1000L) );
+ SUBTEST("signed long multiplication"); //Begin with a new test
+ lx = -1L; ly = 0x1000L; CHECK("-1*0x1000", (lx*ly) == -0x1000L );
+ lx = -10L; ly = 0x1000L; CHECK("-10*0x1000", (lx*ly) == -(10*0x1000L) );
}
void sintdiv(void) {
- SUBTEST("int division\n"); //Begin with a new test
- ix = 10; iy = -2; CHECK("pos/neg:\t", (ix/iy) == -5 );
- ix = -10; iy = 2; CHECK("neg/pos:\t", (ix/iy) == -5 );
- ix = 10; iy = 2; CHECK("pos/pos:\t", (ix/iy) == 5 );
- ix = -10; iy = -2; CHECK("neg/neg:\t", (ix/iy) == 5 );
+ SUBTEST("int division"); //Begin with a new test
+ ix = 10; iy = -2; CHECK("pos/neg", (ix/iy) == -5 );
+ ix = -10; iy = 2; CHECK("neg/pos", (ix/iy) == -5 );
+ ix = 10; iy = 2; CHECK("pos/pos", (ix/iy) == 5 );
+ ix = -10; iy = -2; CHECK("neg/neg", (ix/iy) == 5 );
}
void slongdiv(void) {
- SUBTEST("signed long division\n"); //Begin with a new test
- lx = 10L; ly = -2L; CHECK("10/-2:\t\t\t", (lx/ly) == -5 );
- lx = 0x10000000L; ly = -0x100L; CHECK("0x10000000L/-0x100L:\t", (lx/ly) == -0x100000L );
+ SUBTEST("signed long division"); //Begin with a new test
+ lx = 10L; ly = -2L; CHECK("10/-2", (lx/ly) == -5 );
+ lx = 0x10000000L; ly = -0x100L; CHECK("0x10000000L/-0x100L", (lx/ly) == -0x100000L );
- lx = -10L;ly = 2L; CHECK("-10/2:\t\t\t", (lx/ly) == -5 );
- lx = -0x10000000L; ly = 0x100L; CHECK("-0x10000000L/0x100L:\t", (lx/ly) == -0x100000L );
+ lx = -10L;ly = 2L; CHECK("-10/2", (lx/ly) == -5 );
+ lx = -0x10000000L; ly = 0x100L; CHECK("-0x10000000L/0x100L", (lx/ly) == -0x100000L );
- lx = 10L; ly = 2L; CHECK("10/2:\t\t\t", (lx/ly) == 5 );
- lx = 0x10000000L; ly = 0x100L; CHECK("0x10000000L/0x100L:\t", (lx/ly) == 0x100000L );
+ lx = 10L; ly = 2L; CHECK("10/2", (lx/ly) == 5 );
+ lx = 0x10000000L; ly = 0x100L; CHECK("0x10000000L/0x100L", (lx/ly) == 0x100000L );
- lx = -10L;ly = -2L; CHECK("-10/-2:\t\t\t", (lx/ly) == 5 );
- lx = -0x10000000L; ly = -0x100L; CHECK("-0x10000000L/-0x100L:\t", (lx/ly) == 0x100000L );
+ lx = -10L;ly = -2L; CHECK("-10/-2", (lx/ly) == 5 );
+ lx = -0x10000000L; ly = -0x100L; CHECK("-0x10000000L/-0x100L", (lx/ly) == 0x100000L );
}
void ulongdiv(void) {
- SUBTEST("unsigned long division\n"); //Begin with a new test
- ulx = 10L;uly = 2L; CHECK("10/2:\t\t", (ulx/uly) == 5 );
- ulx = 11L;uly = 2L; CHECK("11/2:\t\t", (ulx/uly) == 5 );
- ulx = 1234L;uly = 1234L;CHECK("1234/1234:\t", (ulx/uly) == 1 );
- ulx = 12345L;uly = 12345L;CHECK("12345/12345:\t", (ulx/uly) == 1 );
- ulx = 0L;uly = 99L; CHECK("0/99:\t\t", (ulx/uly) == 0 );
- ulx = 27L;uly = 4L; CHECK("27/4:\t\t", (ulx/uly) == 6 );
+ SUBTEST("unsigned long division"); //Begin with a new test
+ ulx = 10L;uly = 2L; CHECK("10/2", (ulx/uly) == 5 );
+ ulx = 11L;uly = 2L; CHECK("11/2", (ulx/uly) == 5 );
+ ulx = 1234L;uly = 1234L;CHECK("1234/1234", (ulx/uly) == 1 );
+ ulx = 12345L;uly = 12345L;CHECK("12345/12345", (ulx/uly) == 1 );
+ ulx = 0L;uly = 99L; CHECK("0/99", (ulx/uly) == 0 );
+ ulx = 27L;uly = 4L; CHECK("27/4", (ulx/uly) == 6 );
}
void ulongshl(void) {
- SUBTEST("unsigned long shift left\n"); //Begin with a new test
+ SUBTEST("unsigned long shift left"); //Begin with a new test
ulx = 1L;
- CHECK("1<<0:\t\t", (ulx<<0) == 1L );
- CHECK("1<<1:\t\t", (ulx<<1) == 2L );
- CHECK("1<<2:\t\t", (ulx<<2) == 4L );
- CHECK("1<<3:\t\t", (ulx<<3) == 8L );
- CHECK("1<<5:\t\t", (ulx<<5) == 32L );
- CHECK("1<<8:\t\t", (ulx<<8) == 256L );
- CHECK("1<<11:\t\t", (ulx<<11) == 2048L );
- CHECK("1<<12:\t\t", (ulx<<12) == 4096L );
- CHECK("1<<15:\t\t", (ulx<<15) == 32768L );
- CHECK("1<<16:\t\t", (ulx<<16) == 65536L );
- CHECK("1<<20:\t\t", (ulx<<20) == 1048576L );
- CHECK("1<<31:\t\t", (ulx<<31) == 2147483648L );
- CHECK("1<<32:\t\t", (ulx<<32) == 0 );
+ CHECK("1<<0", (ulx<<0) == 1L );
+ CHECK("1<<1", (ulx<<1) == 2L );
+ CHECK("1<<2", (ulx<<2) == 4L );
+ CHECK("1<<3", (ulx<<3) == 8L );
+ CHECK("1<<5", (ulx<<5) == 32L );
+ CHECK("1<<8", (ulx<<8) == 256L );
+ CHECK("1<<11", (ulx<<11) == 2048L );
+ CHECK("1<<12", (ulx<<12) == 4096L );
+ CHECK("1<<15", (ulx<<15) == 32768L );
+ CHECK("1<<16", (ulx<<16) == 65536L );
+ CHECK("1<<20", (ulx<<20) == 1048576L );
+ CHECK("1<<31", (ulx<<31) == 2147483648L );
+ CHECK("1<<32", (ulx<<32) == 0 );
}
void slongshl(void) {
- SUBTEST("signed long shift left\n"); //Begin with a new test
+ SUBTEST("signed long shift left"); //Begin with a new test
lx = 1L;
- CHECK("1<<0:\t\t", (lx<<0) == 1L );
- CHECK("1<<1:\t\t", (lx<<1) == 2L );
- CHECK("1<<2:\t\t", (lx<<2) == 4L );
- CHECK("1<<3:\t\t", (lx<<3) == 8L );
- CHECK("1<<5:\t\t", (lx<<5) == 32L );
- CHECK("1<<8:\t\t", (lx<<8) == 256L );
- CHECK("1<<11:\t\t", (lx<<11) == 2048L );
- CHECK("1<<12:\t\t", (lx<<12) == 4096L );
- CHECK("1<<15:\t\t", (lx<<15) == 32768L );
- CHECK("1<<16:\t\t", (lx<<16) == 65536L );
- CHECK("1<<20:\t\t", (lx<<20) == 1048576L );
- CHECK("1<<31:\t\t", (lx<<31) == 2147483648L );
- CHECK("1<<32:\t\t", (lx<<32) == 0 );
+ CHECK("1<<0", (lx<<0) == 1L );
+ CHECK("1<<1", (lx<<1) == 2L );
+ CHECK("1<<2", (lx<<2) == 4L );
+ CHECK("1<<3", (lx<<3) == 8L );
+ CHECK("1<<5", (lx<<5) == 32L );
+ CHECK("1<<8", (lx<<8) == 256L );
+ CHECK("1<<11", (lx<<11) == 2048L );
+ CHECK("1<<12", (lx<<12) == 4096L );
+ CHECK("1<<15", (lx<<15) == 32768L );
+ CHECK("1<<16", (lx<<16) == 65536L );
+ CHECK("1<<20", (lx<<20) == 1048576L );
+ CHECK("1<<31", (lx<<31) == 2147483648L );
+ CHECK("1<<32", (lx<<32) == 0 );
}
void usintshl(void) {
- SUBTEST("unsigned int shift left\n"); //Begin with a new test
+ SUBTEST("unsigned int shift left"); //Begin with a new test
uix = 1;
- CHECK("1<<0:\t\t", (uix<<0) == 1 );
- CHECK("1<<1:\t\t", (uix<<1) == 2 );
- CHECK("1<<2:\t\t", (uix<<2) == 4 );
- CHECK("1<<3:\t\t", (uix<<3) == 8 );
- CHECK("1<<5:\t\t", (uix<<5) == 32 );
- CHECK("1<<8:\t\t", (uix<<8) == 256 );
- CHECK("1<<11:\t\t", (uix<<11) == 2048 );
- CHECK("1<<12:\t\t", (uix<<12) == 4096 );
- CHECK("1<<15:\t\t", (uix<<15) == 32768 );
- CHECK("1<<16:\t\t", (uix<<16) == 0 );
+ CHECK("1<<0", (uix<<0) == 1 );
+ CHECK("1<<1", (uix<<1) == 2 );
+ CHECK("1<<2", (uix<<2) == 4 );
+ CHECK("1<<3", (uix<<3) == 8 );
+ CHECK("1<<5", (uix<<5) == 32 );
+ CHECK("1<<8", (uix<<8) == 256 );
+ CHECK("1<<11", (uix<<11) == 2048 );
+ CHECK("1<<12", (uix<<12) == 4096 );
+ CHECK("1<<15", (uix<<15) == 32768 );
+ CHECK("1<<16", (uix<<16) == 0 );
}
void sintshl(void) {
- SUBTEST("signed int shift left\n"); //Begin with a new test
+ SUBTEST("signed int shift left"); //Begin with a new test
ix = 1;
- CHECK("1<<0:\t\t", (ix<<0) == 1 );
- CHECK("1<<1:\t\t", (ix<<1) == 2 );
- CHECK("1<<2:\t\t", (ix<<2) == 4 );
- CHECK("1<<3:\t\t", (ix<<3) == 8 );
- CHECK("1<<5:\t\t", (ix<<5) == 32 );
- CHECK("1<<8:\t\t", (ix<<8) == 256 );
- CHECK("1<<11:\t\t", (ix<<11) == 2048 );
- CHECK("1<<12:\t\t", (ix<<12) == 4096 );
- CHECK("1<<15:\t\t", (ix<<15) == 1<<15 ); //32768
- CHECK("1<<16:\t\t", (ix<<16) == 0 );
+ CHECK("1<<0", (ix<<0) == 1 );
+ CHECK("1<<1", (ix<<1) == 2 );
+ CHECK("1<<2", (ix<<2) == 4 );
+ CHECK("1<<3", (ix<<3) == 8 );
+ CHECK("1<<5", (ix<<5) == 32 );
+ CHECK("1<<8", (ix<<8) == 256 );
+ CHECK("1<<11", (ix<<11) == 2048 );
+ CHECK("1<<12", (ix<<12) == 4096 );
+ CHECK("1<<15", (ix<<15) == 1<<15 ); //32768
+ CHECK("1<<16", (ix<<16) == 0 );
}
void usintshr(void) {
- SUBTEST("unsigned int shift right\n"); //Begin with a new test
+ SUBTEST("unsigned int shift right"); //Begin with a new test
uix = 0x8000;
- CHECK("0x8000>>0:\t", (uix>>0) == 0x8000 );
- CHECK("0x8000>>1:\t", (uix>>1) == 0x4000 );
- CHECK("0x8000>>2:\t", (uix>>2) == 0x2000 );
- CHECK("0x8000>>3:\t", (uix>>3) == 0x1000 );
- CHECK("0x8000>>5:\t", (uix>>5) == 0x0400);
- CHECK("0x8000>>8:\t", (uix>>8) == 0x0080);
- CHECK("0x8000>>11:\t", (uix>>11) == 0x0010 );
- CHECK("0x8000>>12:\t", (uix>>12) == 0x0008 );
- CHECK("0x8000>>15:\t", (uix>>15) == 0x0001 );
- CHECK("0x8000>>16:\t", (uix>>16) == 0 );
+ CHECK("0x8000>>0", (uix>>0) == 0x8000 );
+ CHECK("0x8000>>1", (uix>>1) == 0x4000 );
+ CHECK("0x8000>>2", (uix>>2) == 0x2000 );
+ CHECK("0x8000>>3", (uix>>3) == 0x1000 );
+ CHECK("0x8000>>5", (uix>>5) == 0x0400);
+ CHECK("0x8000>>8", (uix>>8) == 0x0080);
+ CHECK("0x8000>>11", (uix>>11) == 0x0010 );
+ CHECK("0x8000>>12", (uix>>12) == 0x0008 );
+ CHECK("0x8000>>15", (uix>>15) == 0x0001 );
+ CHECK("0x8000>>16", (uix>>16) == 0 );
}
void sintshr(void) {
- SUBTEST("signed int shift right\n"); //Begin with a new test
+ SUBTEST("signed int shift right"); //Begin with a new test
ix = 0x8000;
- CHECK("0x8000>>0:\t", (ix>>0) == 0x8000 );
- CHECK("0x8000>>1:\t", (ix>>1) == 0xC000 );
- CHECK("0x8000>>2:\t", (ix>>2) == 0xE000 );
- CHECK("0x8000>>3:\t", (ix>>3) == 0xF000 );
- CHECK("0x8000>>5:\t", (ix>>5) == 0xFC00);
- CHECK("0x8000>>8:\t", (ix>>8) == 0xFF80);
- CHECK("0x8000>>11:\t", (ix>>11) == 0xFFF0 );
- CHECK("0x8000>>12:\t", (ix>>12) == 0xFFF8 );
- CHECK("0x8000>>15:\t", (ix>>15) == 0xFFFF );
- CHECK("0x8000>>16:\t", (ix>>16) == 0xFFFF );
+ CHECK("0x8000>>0", (ix>>0) == 0x8000 );
+ CHECK("0x8000>>1", (ix>>1) == 0xC000 );
+ CHECK("0x8000>>2", (ix>>2) == 0xE000 );
+ CHECK("0x8000>>3", (ix>>3) == 0xF000 );
+ CHECK("0x8000>>5", (ix>>5) == 0xFC00);
+ CHECK("0x8000>>8", (ix>>8) == 0xFF80);
+ CHECK("0x8000>>11", (ix>>11) == 0xFFF0 );
+ CHECK("0x8000>>12", (ix>>12) == 0xFFF8 );
+ CHECK("0x8000>>15", (ix>>15) == 0xFFFF );
+ CHECK("0x8000>>16", (ix>>16) == 0xFFFF );
}
int main() {
- TEST("Example tests for mspgcc\n"); //all test files MUST start with that one
+ TEST("Example tests for mspgcc"); //all test files MUST start with that one
subt1();
slongmul();
-------------------------------------------------------
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