CVS: msp430-libc/include/msp430 adc10.h,1.6,1.7 adc12.h,1.9,1.10 common.h,1.4,1.5 dma.h,1.4,1.5 sd16.h,1.6,1.7 usart.h,1.9,1.10 usi.h,1.1,1.2
Chris Liechti <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430-libc/include/msp430 In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv31722/msp430-libc/include/msp430 Modified Files: adc10.h adc12.h common.h dma.h sd16.h usart.h usi.h Log Message: - re-add old definitions. thats useful where people are using different versions of gcc to compile projects and makes migration from old to new easier. - added more aliases Index: adc10.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/adc10.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -w -d -r1.6 -r1.7 --- adc10.h 3 Feb 2004 02:10:34 -0000 1.6 +++ adc10.h 12 Jan 2006 00:47:21 -0000 1.7 @@ -124,18 +124,18 @@ #define SHS_2 (2<<10) /* TA3 OUT0 */ #define SHS_3 (3<<10) /* TA3 OUT2 */ -#define INCH_0 (0<<12) -#define INCH_1 (1<<12) -#define INCH_2 (2<<12) -#define INCH_3 (3<<12) -#define INCH_4 (4<<12) -#define INCH_5 (5<<12) -#define INCH_6 (6<<12) -#define INCH_7 (7<<12) -#define INCH_8 (8<<12) -#define INCH_9 (9<<12) -#define INCH_10 (10<<12) -#define INCH_11 (11<<12) +#define INCH_0 (0<<12) /* A0 */ +#define INCH_1 (1<<12) /* A1 */ +#define INCH_2 (2<<12) /* A2 */ +#define INCH_3 (3<<12) /* A3 */ +#define INCH_4 (4<<12) /* A4 */ +#define INCH_5 (5<<12) /* A5 */ +#define INCH_6 (6<<12) /* A6 */ +#define INCH_7 (7<<12) /* A7 */ +#define INCH_8 (8<<12) /* VeREF+ */ +#define INCH_9 (9<<12) /* VREF-/VeREF- */ +#define INCH_10 (10<<12) /* Temperature sensor */ +#define INCH_11 (11<<12) /* (VCC VSS) / 2 */ #define INCH_12 (12<<12) /* Selects channel 11 */ #define INCH_13 (13<<12) /* Selects channel 11 */ #define INCH_14 (14<<12) /* Selects channel 11 */ @@ -148,4 +148,37 @@ #define ADC10DISABLE 0x0000 /* ADC10DTC1 */ +/* Aliases by mspgcc */ +#define ADC10SHT_DIV4 ADC10SHT_0 /* 4 x ADC10CLKs */ +#define ADC10SHT_DIV8 ADC10SHT_1 /* 8 x ADC10CLKs */ +#define ADC10SHT_DIV16 ADC10SHT_2 /* 16 x ADC10CLKs */ +#define ADC10SHT_DIV64 ADC10SHT_3 /* 64 x ADC10CLKs */ + +#define SREF_AVCC_AVSS SREF_0 /* VR+ = AVCC and VR- = AVSS */ +#define SREF_VREF_AVSS SREF_1 /* VR+ = VREF+ and VR- = AVSS */ +#define SREF_VEREF_AVSS SREF_2 /* VR+ = VEREF+ and VR- = AVSS */ +//~ #define SREF_VEREF_AVSS SREF_3 /* VR+ = VEREF+ and VR- = AVSS */ +#define SREF_AVCC_VEREF SREF_4 /* VR+ = AVCC and VR- = VREF-/VEREF- */ +#define SREF_VREF_VEREF SREF_5 /* VR+ = VREF+ and VR- = VREF-/VEREF- */ +#define SREF_VEREF_VEREF SREF_6 /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ +//~ #define SREF_VEREF_VEREF SREF_7 /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ + +#define ADC10SSEL_ADC10OSC ADC10SSEL_0 /* ADC10OSC */ +#define ADC10SSEL_ACLK ADC10SSEL_1 /* ACLK */ +#define ADC10SSEL_MCLK ADC10SSEL_2 /* MCLK */ +#define ADC10SSEL_SMCLK ADC10SSEL_3 /* SMCLK */ + +#define INCH_A0 INCH_0 /* A0 */ +#define INCH_A1 INCH_1 /* A1 */ +#define INCH_A2 INCH_2 /* A2 */ +#define INCH_A3 INCH_3 /* A3 */ +#define INCH_A4 INCH_4 /* A4 */ +#define INCH_A5 INCH_5 /* A5 */ +#define INCH_A6 INCH_6 /* A6 */ +#define INCH_A7 INCH_7 /* A7 */ +#define INCH_VEREF_PLUS INCH_8 /* VeREF+ */ +#define INCH_VEREF_MINUS INCH_9 /* VREF-/VeREF- */ +#define INCH_TEMP INCH_10 /* Temperature sensor */ +#define INCH_VCC2 INCH_11 /* (VCC VSS) / 2 */ + #endif Index: adc12.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/adc12.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -w -d -r1.9 -r1.10 --- adc12.h 15 Jun 2004 13:50:15 -0000 1.9 +++ adc12.h 12 Jan 2006 00:47:21 -0000 1.10 @@ -187,39 +187,39 @@ #define SHT12 0x4000 /* ADC12 Sample Hold 2 Select 2 */ #define SHT13 0x8000 /* ADC12 Sample Hold 3 Select 3 */ -#define SHT0_0 (0<<8) -#define SHT0_1 (1<<8) -#define SHT0_2 (2<<8) -#define SHT0_3 (3<<8) -#define SHT0_4 (4<<8) -#define SHT0_5 (5<<8) -#define SHT0_6 (6<<8) -#define SHT0_7 (7<<8) -#define SHT0_8 (8<<8) -#define SHT0_9 (9<<8) -#define SHT0_10 (10<<8) -#define SHT0_11 (11<<8) -#define SHT0_12 (12<<8) -#define SHT0_13 (13<<8) -#define SHT0_14 (14<<8) -#define SHT0_15 (15<<8) +#define SHT0_0 (0<<8) /* 4 */ +#define SHT0_1 (1<<8) /* 8 */ +#define SHT0_2 (2<<8) /* 16 */ +#define SHT0_3 (3<<8) /* 32 */ +#define SHT0_4 (4<<8) /* 64 */ +#define SHT0_5 (5<<8) /* 96 */ +#define SHT0_6 (6<<8) /* 128 */ +#define SHT0_7 (7<<8) /* 192 */ +#define SHT0_8 (8<<8) /* 256 */ +#define SHT0_9 (9<<8) /* 384 */ +#define SHT0_10 (10<<8) /* 512 */ +#define SHT0_11 (11<<8) /* 768 */ +#define SHT0_12 (12<<8) /* 1024 */ +#define SHT0_13 (13<<8) /* 1024 */ +#define SHT0_14 (14<<8) /* 1024 */ +#define SHT0_15 (15<<8) /* 1024 */ -#define SHT1_0 (0<<12) -#define SHT1_1 (1<<12) -#define SHT1_2 (2<<12) -#define SHT1_3 (3<<12) -#define SHT1_4 (4<<12) -#define SHT1_5 (5<<12) -#define SHT1_6 (6<<12) -#define SHT1_7 (7<<12) -#define SHT1_8 (8<<12) -#define SHT1_9 (9<<12) -#define SHT1_10 (10<<12) -#define SHT1_11 (11<<12) -#define SHT1_12 (12<<12) -#define SHT1_13 (13<<12) -#define SHT1_14 (14<<12) -#define SHT1_15 (15<<12) +#define SHT1_0 (0<<12) /* 4 */ +#define SHT1_1 (1<<12) /* 8 */ +#define SHT1_2 (2<<12) /* 16 */ +#define SHT1_3 (3<<12) /* 32 */ +#define SHT1_4 (4<<12) /* 64 */ +#define SHT1_5 (5<<12) /* 96 */ +#define SHT1_6 (6<<12) /* 128 */ +#define SHT1_7 (7<<12) /* 192 */ +#define SHT1_8 (8<<12) /* 256 */ +#define SHT1_9 (9<<12) /* 384 */ +#define SHT1_10 (10<<12) /* 512 */ +#define SHT1_11 (11<<12) /* 768 */ +#define SHT1_12 (12<<12) /* 1024 */ +#define SHT1_13 (13<<12) /* 1024 */ +#define SHT1_14 (14<<12) /* 1024 */ +#define SHT1_15 (15<<12) /* 1024 */ /* ADC12CTL1 */ #define ADC12BUSY 0x0001 /* ADC12 Busy */ @@ -239,14 +239,14 @@ #define CSTARTADD2 0x4000 /* ADC12 Conversion Start Address 2 */ #define CSTARTADD3 0x8000 /* ADC12 Conversion Start Address 3 */ -#define CONSEQ_0 (0<<1) -#define CONSEQ_1 (1<<1) -#define CONSEQ_2 (2<<1) -#define CONSEQ_3 (3<<1) -#define ADC12SSEL_0 (0<<3) -#define ADC12SSEL_1 (1<<3) -#define ADC12SSEL_2 (2<<3) -#define ADC12SSEL_3 (3<<3) +#define CONSEQ_0 (0<<1) /* Single-channel, single-conversion */ +#define CONSEQ_1 (1<<1) /* Sequence-of-channels */ +#define CONSEQ_2 (2<<1) /* Repeat-single-channel */ +#define CONSEQ_3 (3<<1) /* Repeat-sequence-of-channels */ +#define ADC12SSEL_0 (0<<3) /* ADC12OSC */ +#define ADC12SSEL_1 (1<<3) /* ACLK */ +#define ADC12SSEL_2 (2<<3) /* MCLK */ +#define ADC12SSEL_3 (3<<3) /* SMCLK */ #define ADC12DIV_0 (0<<5) #define ADC12DIV_1 (1<<5) #define ADC12DIV_2 (2<<5) @@ -255,10 +255,10 @@ #define ADC12DIV_5 (5<<5) #define ADC12DIV_6 (6<<5) #define ADC12DIV_7 (7<<5) -#define SHS_0 (0<<10) -#define SHS_1 (1<<10) -#define SHS_2 (2<<10) -#define SHS_3 (3<<10) +#define SHS_0 (0<<10) /* ADC12SC bit */ +#define SHS_1 (1<<10) /* Timer_A.OUT1 */ +#define SHS_2 (2<<10) /* Timer_B.OUT0 */ +#define SHS_3 (3<<10) /* Timer_B.OUT1 */ #define CSTARTADD_0 (0<<12) #define CSTARTADD_1 (1<<12) #define CSTARTADD_2 (2<<12) @@ -277,31 +277,97 @@ #define CSTARTADD_15 (15<<12) /* ADC12MCTLx */ -#define INCH_0 0 -#define INCH_1 1 -#define INCH_2 2 -#define INCH_3 3 -#define INCH_4 4 -#define INCH_5 5 -#define INCH_6 6 -#define INCH_7 7 -#define INCH_8 8 -#define INCH_9 9 -#define INCH_10 10 -#define INCH_11 11 -#define INCH_12 12 -#define INCH_13 13 -#define INCH_14 14 -#define INCH_15 15 +#define INCH_0 0 /* A0 */ +#define INCH_1 1 /* A1 */ +#define INCH_2 2 /* A2 */ +#define INCH_3 3 /* A3 */ +#define INCH_4 4 /* A4 */ +#define INCH_5 5 /* A5 */ +#define INCH_6 6 /* A6 */ +#define INCH_7 7 /* A7 */ +#define INCH_8 8 /* VeREF+ */ +#define INCH_9 9 /* VREF/VeREF */ +#define INCH_10 10 /* Temperature diode */ +#define INCH_11 11 /* (AVCC AVSS) / 2 */ +#define INCH_12 12 /* (AVCC AVSS) / 2 */ +#define INCH_13 13 /* (AVCC AVSS) / 2 */ +#define INCH_14 14 /* (AVCC AVSS) / 2 */ +#define INCH_15 15 /* (AVCC AVSS) / 2 */ -#define SREF_0 (0<<4) -#define SREF_1 (1<<4) -#define SREF_2 (2<<4) -#define SREF_3 (3<<4) -#define SREF_4 (4<<4) -#define SREF_5 (5<<4) -#define SREF_6 (6<<4) -#define SREF_7 (7<<4) +#define SREF_0 (0<<4) /* VR+ = AVCC and VR = AVSS */ +#define SREF_1 (1<<4) /* VR+ = VREF+ and VR = AVSS */ +#define SREF_2 (2<<4) /* VR+ = VeREF+ and VR = AVSS */ +#define SREF_3 (3<<4) /* VR+ = VeREF+ and VR = AVSS */ +#define SREF_4 (4<<4) /* VR+ = AVCC and VR = VREF/ VeREF */ +#define SREF_5 (5<<4) /* VR+ = VREF+ and VR = VREF/ VeREF */ +#define SREF_6 (6<<4) /* VR+ = VeREF+ and VR = VREF/ VeREF */ +#define SREF_7 (7<<4) /* VR+ = VeREF+ and VR = VREF/ VeREF */ #define EOS 0x80 +/* Aliases by mspgcc */ +#define SHT0_DIV4 SHT0_0 /* 4 */ +#define SHT0_DIV8 SHT0_1 /* 8 */ +#define SHT0_DIV16 SHT0_2 /* 16 */ +#define SHT0_DIV32 SHT0_3 /* 32 */ +#define SHT0_DIV64 SHT0_4 /* 64 */ +#define SHT0_DIV96 SHT0_5 /* 96 */ +#define SHT0_DIV128 SHT0_6 /* 128 */ +#define SHT0_DIV192 SHT0_7 /* 192 */ +#define SHT0_DIV256 SHT0_8 /* 256 */ +#define SHT0_DIV384 SHT0_9 /* 384 */ +#define SHT0_DIV512 SHT0_10 /* 512 */ +#define SHT0_DIV768 SHT0_11 /* 768 */ +#define SHT0_DIV1024 SHT0_12 /* 1024 */ + +#define SHT1_DIV4 SHT1_0 /* 4 */ +#define SHT1_DIV8 SHT1_1 /* 8 */ +#define SHT1_DIV16 SHT1_2 /* 16 */ +#define SHT1_DIV32 SHT1_3 /* 32 */ +#define SHT1_DIV64 SHT1_4 /* 64 */ +#define SHT1_DIV96 SHT1_5 /* 96 */ +#define SHT1_DIV128 SHT1_6 /* 128 */ +#define SHT1_DIV192 SHT1_7 /* 192 */ +#define SHT1_DIV256 SHT1_8 /* 256 */ +#define SHT1_DIV384 SHT1_9 /* 384 */ +#define SHT1_DIV512 SHT1_10 /* 512 */ +#define SHT1_DIV768 SHT1_11 /* 768 */ +#define SHT1_DIV1024 SHT1_12 /* 1024 */ + +#define CONSEQ_SINGLE CONSEQ_0 /* Single-channel, single-conversion */ +#define CONSEQ_SEQUENCE CONSEQ_1 /* Sequence-of-channels */ +#define CONSEQ_REPEAT_SINGLE CONSEQ_2 /* Repeat-single-channel */ +#define CONSEQ_REPEAT_SEQUENCE CONSEQ_3 /* Repeat-sequence-of-channels */ +#define ADC12SSEL_ADC12OSC ADC12SSEL_0 /* ADC12OSC */ +#define ADC12SSEL_ACLK ADC12SSEL_1 /* ACLK */ +#define ADC12SSEL_MCLK ADC12SSEL_2 /* MCLK */ +#define ADC12SSEL_SMCLK ADC12SSEL_3 /* SMCLK */ +#define SHS_ADC12SC SHS_0 /* ADC12SC bit */ +#define SHS_TACCR1 SHS_1 /* Timer_A.OUT1 */ +#define SHS_TBCCR0 SHS_2 /* Timer_B.OUT0 */ +#define SHS_TBCCR1 SHS_3 /* Timer_B.OUT1 */ + +#define INCH_A0 0 /* A0 */ +#define INCH_A1 1 /* A1 */ +#define INCH_A2 2 /* A2 */ +#define INCH_A3 3 /* A3 */ +#define INCH_A4 4 /* A4 */ +#define INCH_A5 5 /* A5 */ +#define INCH_A6 6 /* A6 */ +#define INCH_A7 7 /* A7 */ +#define INCH_VEREF_PLUS 8 /* VeREF+ */ +#define INCH_VEREF_MINUS 9 /* VREF/VeREF */ +#define INCH_TEMP 10 /* Temperature diode */ +#define INCH_VCC2 11 /* (AVCC AVSS) / 2 */ + + +#define SREF_AVCC_AVSS SREF_0 /* VR+ = AVCC and VR = AVSS */ +#define SREF_VREF_AVSS SREF_1 /* VR+ = VREF+ and VR = AVSS */ +#define SREF_VEREF_AVSS SREF_2 /* VR+ = VeREF+ and VR = AVSS */ +//~ #define SREF_VEREF_AVSS SREF_3 /* VR+ = VeREF+ and VR = AVSS */ +#define SREF_AVCC_VEREF SREF_4 /* VR+ = AVCC and VR = VREF/ VeREF */ +#define SREF_VREF_VEREF SREF_5 /* VR+ = VREF+ and VR = VREF/ VeREF */ +#define SREF_VEREF_VEREF SREF_6 /* VR+ = VeREF+ and VR = VREF/ VeREF */ +//~ #define SREF_VEREF_VEREF SREF_7 /* VR+ = VeREF+ and VR = VREF/ VeREF */ + #endif + Index: common.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/common.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -w -d -r1.4 -r1.5 --- common.h 10 Jul 2003 22:29:26 -0000 1.4 +++ common.h 12 Jan 2006 00:47:21 -0000 1.5 @@ -115,4 +115,40 @@ #define WDTIS_2 0x0002 #define WDTIS_3 0x0003 + +/* Backwards compatibility to older versions of the header files. + Please consider using the new names. + */ +#ifdef __MSP430_HAS_PORT1__ + #define __msp430_have_port1 +#endif + +#ifdef __MSP430_HAS_PORT2__ + #define __msp430_have_port2 +#endif + +#ifdef __MSP430_HAS_PORT3__ + #define __msp430_have_port3 +#endif + +#ifdef __MSP430_HAS_PORT4__ + #define __msp430_have_port4 +#endif + +#ifdef __MSP430_HAS_PORT5__ + #define __msp430_have_port5 +#endif + +#ifdef __MSP430_HAS_PORT6__ + #define __msp430_have_port6 +#endif + +#ifdef __MSP430_HAS_UART1__ + #define __msp430_have_usart1 +#endif + +#ifdef __MSP430_HAS_TB7__ + #define __msp430_have_timerb7 +#endif + #endif Index: dma.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/dma.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -w -d -r1.4 -r1.5 --- dma.h 27 Sep 2005 16:16:12 -0000 1.4 +++ dma.h 12 Jan 2006 00:47:21 -0000 1.5 @@ -155,4 +155,60 @@ #define DMADT_6 (6<<12) /* DMA transfer mode 6: interleaved, repeat */ #define DMADT_7 (7<<12) /* DMA transfer mode 7: interleaved, repeat */ + +/* Aliases by mspgcc */ +#define DMADT_SINGLE (0<<12) /* DMA transfer mode 0: single */ +#define DMADT_BLOCK (1<<12) /* DMA transfer mode 1: block */ +#define DMADT_INTERLEAVED (2<<12) /* DMA transfer mode 2: interleaved */ +//~ #define DMADT_3 (3<<12) /* DMA transfer mode 3: interleaved */ +#define DMADT_SINGLEREPEAT (4<<12) /* DMA transfer mode 4: single, repeat */ +#define DMADT_BLOCKREPEAT (5<<12) /* DMA transfer mode 5: block, repeat */ +#define DMADT_INTERLEAVEDREPEAT (6<<12) /* DMA transfer mode 6: interleaved, repeat */ +//~ #define DMADT_7 (7<<12) /* DMA transfer mode 7: interleaved, repeat */ + +#define DMA0TSEL_DMA_REQ (0<<0) /* DMA channel 0 transfer select 0: DMA_REQ */ +#define DMA0TSEL_TACCR2 (1<<0) /* DMA channel 0 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA0TSEL_TBCCR2 (2<<0) /* DMA channel 0 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA0TSEL_I2CRX (3<<0) /* DMA channel 0 transfer select 3: I2C receive */ +#define DMA0TSEL_I2CTX (4<<0) /* DMA channel 0 transfer select 4: I2C transmit */ +#define DMA0TSEL_DAC12 (5<<0) /* DMA channel 0 transfer select 5: DAC12.0IFG */ +#define DMA0TSEL_ADC12 (6<<0) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA0TSEL_TACCR0 (7<<0) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA0TSEL_TBCCR0 (8<<0) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA0TSEL_USART1RX (9<<0) /* DMA channel 0 transfer select 9: UART1 receive */ +#define DMA0TSEL_USART1TX (10<<0) /* DMA channel 0 transfer select 10: UART1 transmit */ +#define DMA0TSEL_MUL (11<<0) /* DMA channel 0 transfer select 11: Multiplier ready */ +//~ #define DMA0TSEL_14 (14<<0) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */ +//~ #define DMA0TSEL_15 (15<<0) /* DMA channel 0 transfer select 15: DMAE0 */ + +#define DMA1TSEL_DMA_REQ (0<<4) /* DMA channel 1 transfer select 0: DMA_REQ */ +#define DMA1TSEL_TACCR2 (1<<4) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA1TSEL_TBCCR2 (2<<4) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA1TSEL_I2CRX (3<<4) /* DMA channel 1 transfer select 3: I2C receive */ +#define DMA1TSEL_I2CTX (4<<4) /* DMA channel 1 transfer select 4: I2C transmit */ +#define DMA1TSEL_DAC12 (5<<4) /* DMA channel 1 transfer select 5: DAC12.0IFG */ +#define DMA1TSEL_ADC12 (6<<4) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA1TSEL_TACCR0 (7<<4) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA1TSEL_TBCCR0 (8<<4) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA1TSEL_USART1RX (9<<4) /* DMA channel 1 transfer select 9: UART1 receive */ +#define DMA1TSEL_USART1TX (10<<4) /* DMA channel 1 transfer select 10: UART1 transmit */ +#define DMA1TSEL_MUL (11<<4) /* DMA channel 1 transfer select 11: Multiplier ready */ +//~ #define DMA1TSEL_14 (14<<4) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */ +//~ #define DMA1TSEL_15 (15<<4) /* DMA channel 1 transfer select 15: DMAE0 */ + +#define DMA2TSEL_DMA_REQ (0<<8) /* DMA channel 2 transfer select 0: DMA_REQ */ +#define DMA2TSEL_TACCR2 (1<<8) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */ +#define DMA2TSEL_TBCCR2 (2<<8) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */ +#define DMA2TSEL_I2CRX (3<<8) /* DMA channel 2 transfer select 3: I2C receive */ +#define DMA2TSEL_I2CTX (4<<8) /* DMA channel 2 transfer select 4: I2C transmit */ +#define DMA2TSEL_DAC12 (5<<8) /* DMA channel 2 transfer select 5: DAC12.0IFG */ +#define DMA2TSEL_ADC12 (6<<8) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */ +#define DMA2TSEL_TACCR0 (7<<8) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */ +#define DMA2TSEL_TBCCR0 (8<<8) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */ +#define DMA2TSEL_USART1RX (9<<8) /* DMA channel 2 transfer select 9: UART1 receive */ +#define DMA2TSEL_USART1TX (10<<8) /* DMA channel 2 transfer select 10: UART1 transmit */ +#define DMA2TSEL_MUL (11<<8) /* DMA channel 2 transfer select 11: Multiplier ready */ +//~ #define DMA2TSEL_14 (14<<8) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */ +//~ #define DMA2TSEL_15 (15<<8) /* DMA channel 2 transfer select 15: DMAE0 */ + #endif Index: sd16.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/sd16.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -w -d -r1.6 -r1.7 --- sd16.h 2 Oct 2005 13:27:30 -0000 1.6 +++ sd16.h 12 Jan 2006 00:47:21 -0000 1.7 @@ -187,4 +187,24 @@ #define AFECCTL2 SD16CCTL02 /* SD16 Channel 2 Control Register */ #endif + +/* Aliases by mspgcc */ +#define SD16DIV_DIV1 SD16DIV_0 /* SD16 Clock Divider Select /1 */ +#define SD16DIV_DIV2 SD16DIV_1 /* SD16 Clock Divider Select /2 */ +#define SD16DIV_DIV4 SD16DIV_2 /* SD16 Clock Divider Select /4 */ +#define SD16DIV_DIV8 SD16DIV_3 /* SD16 Clock Divider Select /8 */ + +#if defined(__msp430_have_sd16a) +#define SD16XDIV_DIV1 SD16XDIV_0 /* SD16 2.Clock Divider Select /1 */ +#define SD16XDIV_DIV2 SD16XDIV_1 /* SD16 2.Clock Divider Select /3 */ +#define SD16XDIV_DIV4 SD16XDIV_2 /* SD16 2.Clock Divider Select /16 */ +#define SD16XDIV_DIV8 SD16XDIV_3 /* SD16 2.Clock Divider Select /48 */ +#endif + +#define SD16SSEL_MCLK SD16SSEL_0 /* AFE Clock Source Select MCLK */ +#define SD16SSEL_SMCLK SD16SSEL_1 /* AFE Clock Source Select SMCLK */ +#define SD16SSEL_ACLK SD16SSEL_2 /* AFE Clock Source Select ACLK */ +#define SD16SSEL_TACLK SD16SSEL_3 /* AFE Clock Source Select TACLK */ + + #endif Index: usart.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/usart.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -w -d -r1.9 -r1.10 --- usart.h 17 Nov 2005 01:11:30 -0000 1.9 +++ usart.h 12 Jan 2006 00:47:21 -0000 1.10 @@ -246,6 +246,18 @@ #define I2CIV_ 0x011C /* I2C interrupt vector */ sfrw(I2CIV, I2CIV_); +/* Backwards compatibility to older versions of the header file. + Please consider using the new name I2CDRB. + */ +#define I2CDR_ 0x0076 /* I2C data for byte access */ +sfrb(I2CDR, I2CDR_); + +/* Aliases by mspgcc */ +#define I2CSSEL_UCLK I2CSSEL_0 /* I2C clock select 0: UCLK */ +#define I2CSSEL_ACLK I2CSSEL_1 /* I2C clock select 1: ACLK */ +#define I2CSSEL_SMCLK I2CSSEL_2 /* I2C clock select 2: SMCLK */ +//~ #define I2CSSEL_SMCLK I2CSSEL_3 /* I2C clock select 3: SMCLK */ + #endif /* __MSP430_HAS_I2C__ */ #if defined(__MSP430_HAS_UART1__) Index: usi.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/usi.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -w -d -r1.1 -r1.2 --- usi.h 2 Oct 2005 13:27:30 -0000 1.1 +++ usi.h 12 Jan 2006 00:47:21 -0000 1.2 @@ -64,23 +64,23 @@ #define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */ #define USISWCLK (0x01) /* USI Software Clock */ -#define USIDIV_0 (0x00) /* USI Clock Divider: 0 */ -#define USIDIV_1 (0x20) /* USI Clock Divider: 1 */ -#define USIDIV_2 (0x40) /* USI Clock Divider: 2 */ -#define USIDIV_3 (0x60) /* USI Clock Divider: 3 */ -#define USIDIV_4 (0x80) /* USI Clock Divider: 4 */ -#define USIDIV_5 (0xA0) /* USI Clock Divider: 5 */ -#define USIDIV_6 (0xC0) /* USI Clock Divider: 6 */ -#define USIDIV_7 (0xE0) /* USI Clock Divider: 7 */ +#define USIDIV_0 (0x00) /* USI Clock Divider: 0 Divide by 1 */ +#define USIDIV_1 (0x20) /* USI Clock Divider: 1 Divide by 2 */ +#define USIDIV_2 (0x40) /* USI Clock Divider: 2 Divide by 4 */ +#define USIDIV_3 (0x60) /* USI Clock Divider: 3 Divide by 8 */ +#define USIDIV_4 (0x80) /* USI Clock Divider: 4 Divide by 16 */ +#define USIDIV_5 (0xA0) /* USI Clock Divider: 5 Divide by 32 */ +#define USIDIV_6 (0xC0) /* USI Clock Divider: 6 Divide by 64 */ +#define USIDIV_7 (0xE0) /* USI Clock Divider: 7 Divide by 128 */ -#define USISSEL_0 (0x00) /* USI Clock Source: 0 */ -#define USISSEL_1 (0x04) /* USI Clock Source: 1 */ -#define USISSEL_2 (0x08) /* USI Clock Source: 2 */ -#define USISSEL_3 (0x0C) /* USI Clock Source: 3 */ -#define USISSEL_4 (0x10) /* USI Clock Source: 4 */ -#define USISSEL_5 (0x14) /* USI Clock Source: 5 */ -#define USISSEL_6 (0x18) /* USI Clock Source: 6 */ -#define USISSEL_7 (0x1C) /* USI Clock Source: 7 */ +#define USISSEL_0 (0x00) /* USI Clock Source: 0 SCLK */ +#define USISSEL_1 (0x04) /* USI Clock Source: 1 ACLK */ +#define USISSEL_2 (0x08) /* USI Clock Source: 2 SMCLK */ +#define USISSEL_3 (0x0C) /* USI Clock Source: 3 SMCLK */ +#define USISSEL_4 (0x10) /* USI Clock Source: 4 USISWCLK bit*/ +#define USISSEL_5 (0x14) /* USI Clock Source: 5 TACCR0 */ +#define USISSEL_6 (0x18) /* USI Clock Source: 6 TACCR1 */ +#define USISSEL_7 (0x1C) /* USI Clock Source: 7 TACCR2 */ #define USISCLREL (0x80) /* USI SCL Released */ #define USI16B (0x40) /* USI 16 Bit Shift Register Enable */ @@ -91,4 +91,23 @@ #define USICNT1 (0x02) /* USI Bit Count 1 */ #define USICNT0 (0x01) /* USI Bit Count 0 */ +/* Aliases by mspgcc */ +#define USIDIV_DIV1 USIDIV_0 /* USI Clock Divider: 0 Divide by 1 */ +#define USIDIV_DIV2 USIDIV_1 /* USI Clock Divider: 1 Divide by 2 */ +#define USIDIV_DIV4 USIDIV_2 /* USI Clock Divider: 2 Divide by 4 */ +#define USIDIV_DIV8 USIDIV_3 /* USI Clock Divider: 3 Divide by 8 */ +#define USIDIV_DIV16 USIDIV_4 /* USI Clock Divider: 4 Divide by 16 */ +#define USIDIV_DIV32 USIDIV_5 /* USI Clock Divider: 5 Divide by 32 */ +#define USIDIV_DIV64 USIDIV_6 /* USI Clock Divider: 6 Divide by 64 */ +#define USIDIV_DIV128 USIDIV_7 /* USI Clock Divider: 7 Divide by 128 */ + +#define USISSEL_SMCLK USISSEL_0 /* USI Clock Source: 0 SCLK */ +#define USISSEL_ACLK USISSEL_1 /* USI Clock Source: 1 ACLK */ +//~ #define USISSEL_2 USISSEL_2 /* USI Clock Source: 2 SMCLK */ +//~ #define USISSEL_3 USISSEL_3 /* USI Clock Source: 3 SMCLK */ +#define USISSEL_USISWCLK USISSEL_4 /* USI Clock Source: 4 USISWCLK bit*/ +#define USISSEL_TACCR0 USISSEL_5 /* USI Clock Source: 5 TACCR0 */ +#define USISSEL_TACCR1 USISSEL_6 /* USI Clock Source: 6 TACCR1 */ +#define USISSEL_TACCR2 USISSEL_7 /* USI Clock Source: 7 TACCR2 */ + #endif ------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. 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