CVS: jtag/msp430 JTAGfunc.c,1.7,1.8 MSP430mspgcc.c,1.14,1.15 funclets.c,1.17,1.18
Chris Liechti <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/jtag/msp430
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv920/jtag/msp430
Modified Files:
JTAGfunc.c MSP430mspgcc.c funclets.c
Log Message:
- some changes to the JTAG code (improve communication reliability)
- update comments, typos
Index: JTAGfunc.c
===================================================================
RCS file: /cvsroot/mspgcc/jtag/msp430/JTAGfunc.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -w -d -r1.7 -r1.8
--- JTAGfunc.c 29 Dec 2005 18:44:19 -0000 1.7
+++ JTAGfunc.c 10 Mar 2006 03:42:13 -0000 1.8
@@ -50,7 +50,10 @@
// Perform fuse check
#ifdef SLOWFUSECHECK_BUG // Silicon bug requires slow check of fuse.
- HIL_TCK(0);
+ HIL_TDI(1);
+ HIL_TMS(1);
+ HIL_TCK(1);
+
HIL_TMS(0);
HIL_DelayMSec(FUSECHECK_DELAY);
HIL_TMS(1);
@@ -208,7 +211,7 @@
}
//----------------------------------------------------------------------------
-/* Load a given address into the target CPU's program counter (PC).
+/* Load a given address into the target CPU's register.
Argument: WORD Addr (destination address)
Result: None
*/
@@ -272,10 +275,10 @@
void HaltCPU(void) {
SetInstrFetch(); // Set CPU into instruction fetch mode
- HIL_TCLK(0); //lch
HIL_JTAG_IR(IR_CNTRL_SIG_16BIT);
HIL_JTAG_DR(0x2401, F_WORD);
HIL_JTAG_IR(IR_DATA_16BIT);
+ HIL_TCLK(1); // F2xx
HIL_JTAG_DR(0x3FFF, F_WORD); // Send JMP $ instruction
HIL_TCLK(NEG_EDGE);
HIL_JTAG_IR(IR_CNTRL_SIG_16BIT);
@@ -416,19 +419,19 @@
void WriteMemQuick(WORD StartAddr, WORD Length, const WORD *DataArray) {
WORD i;
- SetPC(StartAddr - 2);
- HIL_JTAG_IR(IR_DATA_16BIT);
- HIL_TCLK(1); // F2xxx
- HIL_JTAG_DR(JMP_$, F_WORD); // Load "jmp $" instruction for use while HALT'ed.
- HIL_TCLK(POS_EDGE);
+ // Initialize writing:
+ SetPC(StartAddr-4);
+ HaltCPU();
+ HIL_TCLK(0);
HIL_JTAG_IR(IR_CNTRL_SIG_16BIT);
- HIL_JTAG_DR(0x2408, F_WORD); // Set JTAG_HALT bit
+ HIL_JTAG_DR(0x2408, F_WORD); // Set JTAG_HALT bit, RW to write
HIL_JTAG_IR(IR_DATA_QUICK);
for (i = 0; i < Length; i++) {
HIL_JTAG_DR(DataArray[i], F_WORD); // Write data to memory.
- HIL_TCLK(POS_EDGE);
+ HIL_TCLK(NEG_EDGE);
}
+ HIL_TCLK(1);
ReleaseCPU();
}
@@ -473,21 +476,19 @@
void ReadMemQuick(WORD StartAddr, WORD Length, WORD *DataArray) {
WORD i;
- SetPC(StartAddr - 2);
- HIL_JTAG_IR(IR_DATA_16BIT);
- HIL_JTAG_DR(JMP_$, F_WORD); // Load "jmp $" instruction for use while HALT'ed.
- HIL_TCLK(NEG_EDGE);
+ // Initialize reading:
+ SetPC(StartAddr-4);
+ HaltCPU();
+ HIL_TCLK(1);
HIL_JTAG_IR(IR_CNTRL_SIG_16BIT);
- HIL_JTAG_DR(0x2409, F_WORD); // Set JTAG_HALT bit
+ HIL_JTAG_DR(0x2409, F_WORD); // Set RW to read
HIL_JTAG_IR(IR_DATA_QUICK);
for (i = 0; i < Length; i++) {
HIL_TCLK(NEG_EDGE);
DataArray[i] = HIL_JTAG_DR(0, F_WORD); // Read data from memory.
}
HIL_TCLK(1); // F2xxx
- HIL_JTAG_IR(IR_CNTRL_SIG_16BIT);
- HIL_JTAG_DR(0x2401, F_WORD); // Clear the HALT_JTAG bit (Release CPU)
ReleaseCPU();
}
Index: MSP430mspgcc.c
===================================================================
RCS file: /cvsroot/mspgcc/jtag/msp430/MSP430mspgcc.c,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -w -d -r1.14 -r1.15
--- MSP430mspgcc.c 29 Dec 2005 18:45:07 -0000 1.14
+++ MSP430mspgcc.c 10 Mar 2006 03:42:13 -0000 1.15
@@ -310,7 +310,7 @@
// Assert (hard) ~RST/NMI.
HIL_RST(0);
HIL_DelayMSec(50); // keep it low for some time (discharge caps)
- HIL_RST(1); // adds an other delay ater the pin is high
+ HIL_RST(1); // adds an other delay after the pin is high
if (releaseJTAG) {
if (HIL_Release() != STATUS_OK) { // Release the JTAG control signals.
MSP430_Log(2, "MSP430mspgcc: RST_RESET but JTAG release FAILED\n");
Index: funclets.c
===================================================================
RCS file: /cvsroot/mspgcc/jtag/msp430/funclets.c,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -w -d -r1.17 -r1.18
--- funclets.c 1 Feb 2006 23:59:11 -0000 1.17
+++ funclets.c 10 Mar 2006 03:42:14 -0000 1.18
@@ -181,7 +181,7 @@
}
// ----------------------------------------------------------------------------
-#include "ramsizeDetect.ci" //include the counter program
+#include "ramsizeDetect.ci" // include the detection program
/**
* Probe RAM size.
@@ -422,14 +422,14 @@
HIL_StopTimer();
if (runtime != NULL) *runtime = runtime_internal;
// For F413P, F41xC, and F12x devices, the following step will likely corrupt RAM.
- // However, we don't care about this as the RAM contents will be reloaded in necessary.
+ // However, we don't care about this as the RAM contents will be reloaded if necessary.
MSP430_Log(3, "funclets: executeCodeSafe: wait OK (%ums)\n", runtime_internal); //DEBUG
return syncCPU(); // Resume control of the CPU. Read/Write will be set.
}
}
HIL_StopTimer();
// if runtime out parameter is given, exit with success, the caller can
- // test the runtime to see if its OK for him. Otherways fail.
+ // test the runtime to see if it's OK for him. Otherways fail.
if (runtime != NULL) {
*runtime = runtime_internal;
MSP430_Log(3, "funclets: executeCodeSafe: timeout (%ums)\n", runtime_internal); //DEBUG
@@ -465,8 +465,8 @@
MSP430_Log(3, "funclets: executeCode: download %d words...\n", sizeCode); //DEBUG
SetPC(code[0] - 2);
- HIL_JTAG_IR(IR_DATA_16BIT);
HIL_TCLK(1); // F2xxx
+ HIL_JTAG_IR(IR_DATA_16BIT);
HIL_JTAG_DR(JMP_$, F_WORD); // Load "jmp $" instruction for use while HALT'ed.
HIL_TCLK(POS_EDGE);
@@ -506,7 +506,7 @@
for (i = 0; i < sizeCode; i++) { // Verify the memory contents.
if (Read[i] != code[i]) {
free(Read); // Free read buffer
- MSP430_Log(1, "funclets: executeCode: verify error (word %d)\n", i); //DEBUG
+ MSP430_Log(1, "funclets: executeCode: verify error (word %d 0x%04x != 0x%04x)\n", i, Read[i], code[i]); // DEBUG
return STATUS_ERROR;
}
}
@@ -523,7 +523,7 @@
MSP430_Log(5, "funclets: executeCode: set active...\n"); //DEBUG
HIL_JTAG_IR(IR_DATA_16BIT);
HIL_TCLK(1); // F2xxx
- HIL_JTAG_DR(0x4032, 16); // Clear the Status Register (no low power modes, diable irqs).
+ HIL_JTAG_DR(0x4032, 16); // Clear the Status Register (no low power modes, disable irqs).
HIL_TCLK(POS_EDGE);
HIL_JTAG_DR(0, 16);
HIL_TCLK(POS_EDGE);
@@ -548,14 +548,14 @@
HIL_StopTimer();
if (runtime != NULL) *runtime = runtime_internal;
// For F413P, F41xC, and F12x devices, the following step will likely corrupt RAM.
- // However, we don't care about this as the RAM contents will be reloaded in necessary.
+ // However, we don't care about this as the RAM contents will be reloaded if necessary.
MSP430_Log(3, "funclets: executeCode: wait OK (%ums)\n", runtime_internal); //DEBUG
return syncCPU(); // Resume control of the CPU. Read/Write will be set.
}
}
HIL_StopTimer();
- // if runtime out parameter is given, exit iwth success, the caller can
- // test the runtime to see if its OK for him. Otherways fail.
+ // if runtime out parameter is given, exit with success, the caller can
+ // test the runtime to see if it's OK for him. Otherways fail.
if (runtime != NULL) {
*runtime = runtime_internal;
MSP430_Log(3, "funclets: executeCode: timeout (%ums)\n", runtime_internal); //DEBUG
@@ -572,7 +572,7 @@
/**
* Execute a peace of code, a funclet, in the MSP430s RAM.
*
- * We dont have the correct code for a execute code that works with F1xx/F4xx
+ * We don't have the correct code for a execute code that works with F1xx/F4xx
* series with the JTAG bug AND the F2xx devices. Solution: choose one or the
* other executeCode implementation, depending on CPU type.
*
-------------------------------------------------------
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