CVS: msp430-libc/include/msp430 basic_timer.h, 1.4, 1.5 system_clock.h, 1.6, 1.7 usci.h, 1.2, 1.3
Steve Underwood <[email protected]> Wed, 07 Jun 2006 06:01:32 -0700
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430-libc/include/msp430 In directory sc8-pr-cvs7.sourceforge.net:/tmp/cvs-serv13730/msp430-libc/include/msp430 Modified Files: basic_timer.h system_clock.h usci.h Log Message: Several tidyups for module definitions, and USCI 1 added to the USCI header Index: basic_timer.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/basic_timer.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -w -d -r1.4 -r1.5 --- basic_timer.h 23 Apr 2006 16:37:22 -0000 1.4 +++ basic_timer.h 7 Jun 2006 13:01:30 -0000 1.5 @@ -117,10 +117,6 @@ sfrb(RTCNT3, RTCNT3_); #define RTCNT4_ 0x0045 /* Real Time Counter 4 */ sfrb(RTCNT4, RTCNT4_); -#define BTCNT1_ 0x0046 /* Basic Timer Count 1 */ -sfrb(BTCNT1, BTCNT1_); -#define BTCNT2_ 0x0047 /* Basic Timer Count 2 */ -sfrb(BTCNT2, BTCNT2_); #define RTCDAY_ 0x004C /* Real Time Clock Day */ sfrb(RTCDAY, RTCDAY_); #define RTCMON_ 0x004D /* Real Time Clock Month */ Index: system_clock.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/system_clock.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -w -d -r1.6 -r1.7 --- system_clock.h 26 Nov 2003 14:28:11 -0000 1.6 +++ system_clock.h 7 Jun 2006 13:01:30 -0000 1.7 @@ -14,8 +14,9 @@ /* Switches: -__msp430_have_fll - if device has an FLL+ -__msp430_have_fll_and_xt2 - if device has both an FLL+ and a Xtal oscillator 2 +__MSP430_HAS_FLL__ - if device has the original FLL +__MSP430_HAS_FLLPLUS__ - if device has both an FLL+ and a Xtal oscillator 2 +__MSP430_HAS_FLLPLUS_SMALL__- if device has the smaller FLL+ */ @@ -24,7 +25,7 @@ #define FN_2 0x04 #define FN_3 0x08 #define FN_4 0x10 -#if defined(__msp430_have_fll) || defined(__msp430_have_fll_and_xt2) +#if defined(__MSP430_HAS_FLLPLUS__) || defined(__MSP430_HAS_FLLPLUS_SMALL__) #define FN_8 0x20 /* fDCOCLK = 10*fNominal */ #define FLLD0 0x40 /* Loop Divider Bit : 0 */ #define FLLD1 0x80 /* Loop Divider Bit : 1 */ @@ -49,7 +50,7 @@ #define SCFQ_2M 0x3F /* fMCLK=64*fACLK */ #define SCFQ_4M 0x7F /* fMCLK=128*fACLK not possible for ICE */ -#if defined(__msp430_have_fll) || defined(__msp430_have_fll_and_xt2) +#if defined(__MSP430_HAS_FLLPLUS__) || defined(__MSP430_HAS_FLLPLUS_SMALL__) #define SCFQ_M 0x80 /* Modulation Disable */ @@ -58,7 +59,7 @@ #define DCOF 0x01 /* DCO Fault Flag */ #define LFOF 0x02 /* Low Frequency Oscillator Fault Flag */ #define XT1OF 0x04 /* High Frequency Oscillator Fault Flag */ -#if defined(__msp430_have_fll_and_xt2) +#if defined(__MSP430_HAS_FLLPLUS__) #define XT2OF 0x08 /* XT2 Oscillator Fault Flag */ #endif #define XCAP0PF 0x00 /* XIN Cap = XOUT Cap = 0pf */ @@ -78,7 +79,7 @@ #define FLL_DIV_4 0x02 /* FLL+ Divide Px.x/ACLK By 4 */ #define FLL_DIV_8 0x03 /* FLL+ Divide Px.x/ACLK By 8 */ -#if defined(__msp430_have_fll_and_xt2) +#if defined(__MSP430_HAS_FLLPLUS__) #define SELS 0x04 /* Peripheral Module Clock Source (0: DCO, 1: XT2) */ #define SELM0 0x08 /* MCLK Source Select 0 */ #define SELM1 0x10 /* MCLK Source Select 1 */ Index: usci.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/usci.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -w -d -r1.2 -r1.3 --- usci.h 5 Apr 2006 12:06:34 -0000 1.2 +++ usci.h 7 Jun 2006 13:01:30 -0000 1.3 @@ -14,6 +14,8 @@ /* Switches: +__MSP430_HAS_USCI1__ - if device has USCI1 + */ #define USIPE7 (0x80) /* USI Port Enable Px.7 */ @@ -70,57 +72,6 @@ #define USICNT1 (0x02) /* USI Bit Count 1 */ #define USICNT0 (0x01) /* USI Bit Count 0 */ - - - - - - - -#define UCA0CTL0_ 0x0060 /* USCI A0 Control Register 0 */ -sfrb(UCA0CTL0, UCA0CTL0_); -#define UCA0CTL1_ 0x0061 /* USCI A0 Control Register 1 */ -sfrb(UCA0CTL1, UCA0CTL1_); -#define UCA0BR0_ 0x0062 /* USCI A0 Baud Rate 0 */ -sfrb(UCA0BR0, UCA0BR0_); -#define UCA0BR1_ 0x0063 /* USCI A0 Baud Rate 1 */ -sfrb(UCA0BR1, UCA0BR1_); -#define UCA0MCTL_ 0x0064 /* USCI A0 Modulation Control */ -sfrb(UCA0MCTL, UCA0MCTL_); -#define UCA0STAT_ 0x0065 /* USCI A0 Status Register */ -sfrb(UCA0STAT, UCA0STAT_); -#define UCA0RXBUF_ 0x0066 /* USCI A0 Receive Buffer */ -/*READ_ONLY*/ sfrb(UCA0RXBUF, UCA0RXBUF_); -#define UCA0TXBUF_ 0x0067 /* USCI A0 Transmit Buffer */ -sfrb(UCA0TXBUF, UCA0TXBUF_); -#define UCA0ABCTL_ 0x005D /* USCI A0 LIN Control */ -sfrb(UCA0ABCTL, UCA0ABCTL_); -#define UCA0IRTCTL_ 0x005E /* USCI A0 IrDA Transmit Control */ -sfrb(UCA0IRTCTL, UCA0IRTCTL_); -#define UCA0IRRCTL_ 0x005F /* USCI A0 IrDA Receive Control */ -sfrb(UCA0IRRCTL, UCA0IRRCTL_); - -#define UCB0CTL0_ 0x0068 /* USCI B0 Control Register 0 */ -sfrb(UCB0CTL0, UCB0CTL0_); -#define UCB0CTL1_ 0x0069 /* USCI B0 Control Register 1 */ -sfrb(UCB0CTL1, UCB0CTL1_); -#define UCB0BR0_ 0x006A /* USCI B0 Baud Rate 0 */ -sfrb(UCB0BR0, UCB0BR0_); -#define UCB0BR1_ 0x006B /* USCI B0 Baud Rate 1 */ -sfrb(UCB0BR1, UCB0BR1_); -#define UCB0I2CIE_ 0x006C /* USCI B0 I2C Interrupt Enable Register */ -sfrb(UCB0I2CIE, UCB0I2CIE_); -#define UCB0STAT_ 0x006D /* USCI B0 Status Register */ -sfrb(UCB0STAT, UCB0STAT_); -#define UCB0RXBUF_ 0x006E /* USCI B0 Receive Buffer */ -/*READ_ONLY*/ sfrb(UCB0RXBUF, UCB0RXBUF_); -#define UCB0TXBUF_ 0x006F /* USCI B0 Transmit Buffer */ -sfrb(UCB0TXBUF, UCB0TXBUF_); -#define UCB0I2COA_ 0x0118 /* USCI B0 I2C Own Address */ -sfrw(UCB0I2COA, UCB0I2COA_); -#define UCB0I2CSA_ 0x011A /* USCI B0 I2C Slave Address */ -sfrw(UCB0I2CSA, UCB0I2CSA_); - // UART-Mode Bits #define UCPEN (0x80) /* Async. Mode: Parity enable */ #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ @@ -286,4 +237,105 @@ #define UCSA1 (0x0002) /* I2C Slave Address 1 */ #define UCSA0 (0x0001) /* I2C Slave Address 0 */ +/* -------- USCI0 */ + +#define UCA0CTL0_ 0x0060 /* USCI A0 Control Register 0 */ +sfrb(UCA0CTL0, UCA0CTL0_); +#define UCA0CTL1_ 0x0061 /* USCI A0 Control Register 1 */ +sfrb(UCA0CTL1, UCA0CTL1_); +#define UCA0BR0_ 0x0062 /* USCI A0 Baud Rate 0 */ +sfrb(UCA0BR0, UCA0BR0_); +#define UCA0BR1_ 0x0063 /* USCI A0 Baud Rate 1 */ +sfrb(UCA0BR1, UCA0BR1_); +#define UCA0MCTL_ 0x0064 /* USCI A0 Modulation Control */ +sfrb(UCA0MCTL, UCA0MCTL_); +#define UCA0STAT_ 0x0065 /* USCI A0 Status Register */ +sfrb(UCA0STAT, UCA0STAT_); +#define UCA0RXBUF_ 0x0066 /* USCI A0 Receive Buffer */ +/*READ_ONLY*/ sfrb(UCA0RXBUF, UCA0RXBUF_); +#define UCA0TXBUF_ 0x0067 /* USCI A0 Transmit Buffer */ +sfrb(UCA0TXBUF, UCA0TXBUF_); +#define UCA0ABCTL_ 0x005D /* USCI A0 Auto baud/LIN Control */ +sfrb(UCA0ABCTL, UCA0ABCTL_); +#define UCA0IRTCTL_ 0x005E /* USCI A0 IrDA Transmit Control */ +sfrb(UCA0IRTCTL, UCA0IRTCTL_); +#define UCA0IRRCTL_ 0x005F /* USCI A0 IrDA Receive Control */ +sfrb(UCA0IRRCTL, UCA0IRRCTL_); + +#define UCB0CTL0_ 0x0068 /* USCI B0 Control Register 0 */ +sfrb(UCB0CTL0, UCB0CTL0_); +#define UCB0CTL1_ 0x0069 /* USCI B0 Control Register 1 */ +sfrb(UCB0CTL1, UCB0CTL1_); +#define UCB0BR0_ 0x006A /* USCI B0 Baud Rate 0 */ +sfrb(UCB0BR0, UCB0BR0_); +#define UCB0BR1_ 0x006B /* USCI B0 Baud Rate 1 */ +sfrb(UCB0BR1, UCB0BR1_); +#define UCB0I2CIE_ 0x006C /* USCI B0 I2C Interrupt Enable Register */ +sfrb(UCB0I2CIE, UCB0I2CIE_); +#define UCB0STAT_ 0x006D /* USCI B0 Status Register */ +sfrb(UCB0STAT, UCB0STAT_); +#define UCB0RXBUF_ 0x006E /* USCI B0 Receive Buffer */ +/*READ_ONLY*/ sfrb(UCB0RXBUF, UCB0RXBUF_); +#define UCB0TXBUF_ 0x006F /* USCI B0 Transmit Buffer */ +sfrb(UCB0TXBUF, UCB0TXBUF_); +#define UCB0I2COA_ 0x0118 /* USCI B0 I2C Own Address */ +sfrw(UCB0I2COA, UCB0I2COA_); +#define UCB0I2CSA_ 0x011A /* USCI B0 I2C Slave Address */ +sfrw(UCB0I2CSA, UCB0I2CSA_); + +#if defined(__MSP430_HAS_USCI1__) + +/* -------- USCI1 */ + +#define UCA1CTL0_ 0x00D0 /* USCI A1 Control Register 0 */ +sfrb(UCA1CTL0, UCA1CTL0_); +#define UCA1CTL1_ 0x00D1 /* USCI A1 Control Register 1 */ +sfrb(UCA1CTL1, UCA1CTL1_); +#define UCA1BR0_ 0x00D2 /* USCI A1 Baud Rate 0 */ +sfrb(UCA1BR0, UCA1BR0_); +#define UCA1BR1_ 0x00D3 /* USCI A1 Baud Rate 1 */ +sfrb(UCA1BR1, UCA1BR1_); +#define UCA1MCTL_ 0x00D4 /* USCI A1 Modulation Control */ +sfrb(UCA1MCTL, UCA1MCTL_); +#define UCA1STAT_ 0x00D5 /* USCI A1 Status Register */ +sfrb(UCA1STAT, UCA1STAT_); +#define UCA1RXBUF_ 0x00D6 /* USCI A1 Receive Buffer */ +/*READ_ONLY*/ sfrb(UCA1RXBUF, UCA1RXBUF_); +#define UCA1TXBUF_ 0x00D7 /* USCI A1 Transmit Buffer */ +sfrb(UCA1TXBUF, UCA1TXBUF_); +#define UCA1ABCTL_ 0x00CD /* USCI A1 Auto baud/LIN Control */ +sfrb(UCA1ABCTL, UCA1ABCTL_); +#define UCA1IRTCTL_ 0x00CE /* USCI A1 IrDA Transmit Control */ +sfrb(UCA1IRTCTL, UCA1IRTCTL_); +#define UCA1IRRCTL_ 0x00CF /* USCI A1 IrDA Receive Control */ +sfrb(UCA1IRRCTL, UCA1IRRCTL_); + +#define UCB1CTL0_ 0x00D8 /* USCI B1 Control Register 0 */ +sfrb(UCB1CTL0, UCB1CTL0_); +#define UCB1CTL1_ 0x00D9 /* USCI B1 Control Register 1 */ +sfrb(UCB1CTL1, UCB1CTL1_); +#define UCB1BR0_ 0x00DA /* USCI B1 Baud Rate 0 */ +sfrb(UCB1BR0, UCB1BR0_); +#define UCB1BR1_ 0x00DB /* USCI B1 Baud Rate 1 */ +sfrb(UCB1BR1, UCB1BR1_); +#define UCB1I2CIE_ 0x00DC /* USCI B1 I2C Interrupt Enable Register */ +sfrb(UCB1I2CIE, UCB1I2CIE_); +#define UCB1STAT_ 0x00DD /* USCI B1 Status Register */ +sfrb(UCB1STAT, UCB1STAT_); +#define UCB1RXBUF_ 0x00DE /* USCI B1 Receive Buffer */ +/*READ_ONLY*/ sfrb(UCB1RXBUF, UCB1RXBUF_); +#define UCB1TXBUF_ 0x00DF /* USCI B1 Transmit Buffer */ +sfrb(UCB1TXBUF, UCB1TXBUF_); +#define UCB1I2COA_ 0x017C /* USCI B1 I2C Own Address */ +sfrw(UCB1I2COA, UCB1I2COA_); +#define UCB1I2CSA_ 0x017E /* USCI B1 I2C Slave Address */ +sfrw(UCB1I2CSA, UCB1I2CSA_); + +#define UC1IE_ 0x0006 /* USCI A1/B1 Interrupt enable register */ +sfrb(UC1IE, UC1IE_); +#define UC1IFG_ 0x0007 /* USCI A1/B1 Interrupt flag register */ +sfrb(UC1IFG, UC1IFG_); + +#endif /* __MSP430_HAS_USCI1__ */ + #endif