CVS: msp430-libc/include/msp430 dma.h,1.5,1.6

Update of /cvsroot/mspgcc/msp430-libc/include/msp430
In directory sc8-pr-cvs16.sourceforge.net:/tmp/cvs-serv13207/msp430-libc/include/msp430

Modified Files:
	dma.h 
Log Message:
Added sfra as a register type for the MSP430X
Fixed Timer B size for FG461x
Started proper DMAX support, though it has not been checked


Index: dma.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/dma.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -w -d -r1.5 -r1.6
--- dma.h	12 Jan 2006 00:47:21 -0000	1.5
+++ dma.h	17 Jun 2007 15:43:25 -0000	1.6
@@ -18,6 +18,8 @@
 sfrw(DMACTL0,DMACTL0_);
 #define DMACTL1_             0x0124  /* DMA module control 1 */
 sfrw(DMACTL1, DMACTL1_);
+
+#if defined(__MSP430_HAS_DMA_3__)
 #define DMA0CTL_             0x01E0  /* DMA channel 0 control */
 sfrw(DMA0CTL, DMA0CTL_);
 #define DMA0SA_              0x01E2  /* DMA channel 0 source address */
@@ -26,6 +28,7 @@
 sfrw(DMA0DA, DMA0DA_);
 #define DMA0SZ_              0x01E6  /* DMA channel 0 transfer size */
 sfrw(DMA0SZ, DMA0SZ_);
+
 #define DMA1CTL_             0x01E8  /* DMA channel 1 control */
 sfrw(DMA1CTL, DMA1CTL_);
 #define DMA1SA_              0x01EA  /* DMA channel 1 source address */
@@ -34,6 +37,7 @@
 sfrw(DMA1DA, DMA1DA_);
 #define DMA1SZ_              0x01EE  /* DMA channel 1 transfer size */
 sfrw(DMA1SZ, DMA1SZ_);
+
 #define DMA2CTL_             0x01F0  /* DMA channel 2 control */
 sfrw(DMA2CTL, DMA2CTL_);
 #define DMA2SA_              0x01F2  /* DMA channel 2 source address */
@@ -42,6 +46,48 @@
 sfrw(DMA2DA, DMA2DA_);
 #define DMA2SZ_              0x01F6  /* DMA channel 2 transfer size */
 sfrw(DMA2SZ, DMA2SZ_);
+#endif
+
+#if defined(__MSP430_HAS_DMAX_3__)
+#define DMA0CTL_             0x01D0  /* DMA channel 0 control */
+sfrw(DMA0CTL, DMA0CTL_);
+#define DMA0SA_              0x01D2  /* DMA channel 0 source address */
+sfra(DMA0SA, DMA0SA_);
+#define DMA0SAL              0x01D2  /* DMA channel 0 source address */
+sfrw(DMA0SAL, DMA0SAL_);
+#define DMA0DA_              0x01D6  /* DMA channel 0 destination address */
+sfra(DMA0DA, DMA0DA_);
+#define DMA0DAL_             0x01D6  /* DMA channel 0 destination address */
+sfrw(DMA0DAL, DMA0DAL_);
+#define DMA0SZ_              0x01DA  /* DMA channel 0 transfer size */
+sfrw(DMA0SZ, DMA0SZ_);
+
+#define DMA1CTL_             0x01DC  /* DMA channel 1 control */
+sfrw(DMA1CTL, DMA1CTL_);
+#define DMA1SA_              0x01DE  /* DMA channel 1 source address */
+sfra(DMA1SA, DMA1SA_);
+#define DMA1SAL_             0x01DE  /* DMA channel 1 source address */
+sfrw(DMA1SAL, DMA1SAL_);
+#define DMA1DA_              0x01E2  /* DMA channel 1 destination address */
+sfrw(DMA1DA, DMA1DA_);
+#define DMA1DAL              0x01E2  /* DMA channel 1 destination address */
+sfrw(DMA1DAL, DMA1DAL_);
+#define DMA1SZ_              0x01E6  /* DMA channel 1 transfer size */
+sfrw(DMA1SZ, DMA1SZ_);
+
+#define DMA2CTL_             0x01E8  /* DMA channel 2 control */
+sfrw(DMA2CTL, DMA2CTL_);
+#define DMA2SA_              0x01EA  /* DMA channel 2 source address */
+sfra(DMA2SA, DMA2SA_);
+#define DMA2SAL_             0x01EA  /* DMA channel 2 source address */
+sfrw(DMA2SAL, DMA2SAL_);
+#define DMA2DA_              0x01EE  /* DMA channel 2 destination address */
+sfra(DMA2DA, DMA2DA_);
+#define DMA2DAL              0x01EE  /* DMA channel 2 destination address */
+sfrw(DMA2DAL, DMA2DAL_);
+#define DMA2SZ_              0x01F2  /* DMA channel 2 transfer size */
+sfrw(DMA2SZ, DMA2SZ_);
+#endif
 
 #define SREF_0              (0<<4)
 #define SREF_1              (1<<4)


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