CVS: msp430-libc/include msp430x23x.h, NONE, 1.1 msp430x23x0.h, 1.1, 1.2 msp430x24x.h, 1.4, 1.5 msp430x24x1.h, 1.4, 1.5

Update of /cvsroot/mspgcc/msp430-libc/include
In directory sc8-pr-cvs16.sourceforge.net:/tmp/cvs-serv15668

Modified Files:
	msp430x23x0.h msp430x24x.h msp430x24x1.h 
Added Files:
	msp430x23x.h 
Log Message:
- while the devices have theretical support for 64 vectors only 32 are used. the compiler allows to use these for programm code (as noted in the data sheets)
- msp430x23x.h was missing
- add BSLSKEY defs


--- NEW FILE: msp430x23x.h ---
#ifndef __msp430x23x
#define __msp430x23x

/* msp430x23x.h
 *
 * mspgcc project: MSP430 device headers
 * MSP430x23x family header
 *
 * (c) 2007 by Steve Underwood <[email protected]>
 * Originally based in part on work by Texas Instruments Inc.
 *
 * $Id: msp430x23x.h,v 1.1 2008/06/18 00:04:40 cliechti Exp $
 */

#include <iomacros.h>

#define __MSP430_HAS_WDT__
#define __MSP430_HAS_PORT1_R__
#define __MSP430_HAS_PORT2_R__
#define __MSP430_HAS_PORT3_R__
#define __MSP430_HAS_PORT4_R__
#define __MSP430_HAS_PORT5_R__
#define __MSP430_HAS_PORT6_R__
#define __MSP430_HAS_TA3__
#define __MSP430_HAS_TB3__
#define __MSP430_HAS_BC2__
#define __MSP430_HAS_FLASH2__
#define __MSP430_HAS_USCI__
#define __MSP430_HAS_CAPLUS__
#define __MSP430_HAS_MPY__

#include <msp430/basic_clock.h>
#include <msp430/flash.h>
#include <msp430/eprom.h>
#include <msp430/timera.h>
#include <msp430/timerb.h>
#include <msp430/gpio.h>
#include <msp430/usci.h>
#include <msp430/compa.h>
#include <msp430/mpy.h>

#include <msp430/common.h>

#define IE1_                0x0000  /* Interrupt Enable 1 */
sfrb(IE1, IE1_);
#define WDTIE               (1<<0)      /* Watchdog Interrupt Enable */
#define OFIE                (1<<1)      /* Osc. Fault  Interrupt Enable */
#define NMIIE               (1<<4)      /* NMI Interrupt Enable */
#define ACCVIE              (1<<5)      /* Flash Access Violation Interrupt Enable */

#define IFG1_               0x0002  /* Interrupt Flag 1 */
sfrb(IFG1, IFG1_);
#define WDTIFG              (1<<0)      /* Watchdog Interrupt Flag */
#define OFIFG               (1<<1)      /* Osc. Fault Interrupt Flag */
#define PORIFG              (1<<2)      /* Power On Interrupt Flag */
#define RSTIFG              (1<<3)      /* Reset Interrupt Flag */
#define NMIIFG              (1<<4)      /* NMI Interrupt Flag */

#define IE2_                0x0001  /* Interrupt Enable 2 */
sfrb(IE2, IE2_);
#define UCA0RXIE            (1<<0)
#define UCA0TXIE            (1<<1)
#define UCB0RXIE            (1<<2)
#define UCB0TXIE            (1<<3)

#define IFG2_               0x0003  /* Interrupt Flag 2 */
sfrb(IFG2,IFG2_);
#define UCA0RXIFG           (1<<0)
#define UCA0TXIFG           (1<<1)
#define UCB0RXIFG           (1<<2)
#define UCB0TXIFG           (1<<3)

/************************************************************
* Calibration Data in Info Mem
************************************************************/

#ifndef __DisableCalData

#define CALDCO_16MHZ_         0x10F8    /* DCOCTL  Calibration Data for 16MHz */
sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
#define CALBC1_16MHZ_         0x10F9    /* BCSCTL1 Calibration Data for 16MHz */
sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
#define CALDCO_12MHZ_         0x10FA    /* DCOCTL  Calibration Data for 12MHz */
sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
#define CALBC1_12MHZ_         0x10FB    /* BCSCTL1 Calibration Data for 12MHz */
sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
#define CALDCO_8MHZ_          0x10FC    /* DCOCTL  Calibration Data for 8MHz */
sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
#define CALBC1_8MHZ_          0x10FD    /* BCSCTL1 Calibration Data for 8MHz */
sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
#define CALDCO_1MHZ_          0x10FE    /* DCOCTL  Calibration Data for 1MHz */
sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
#define CALBC1_1MHZ_          0x10FF    /* BCSCTL1 Calibration Data for 1MHz */
sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);

#endif /* #ifndef __DisableCalData */

#define USCIAB1TX_VECTOR    0  /* 0xFFE0 USCI A1/B1 Transmit */
#define USCIAB1RX_VECTOR    2  /* 0xFFE2 USCI A1/B1 Receive */
#define PORT1_VECTOR        4  /* 0xFFE4 Port 1 */
#define PORT2_VECTOR        6  /* 0xFFE6 Port 2 */
#define RESERVED20_VECTOR   8  /* 0xFFE8 Reserved Int. Vector 20 */
#define ADC12_VECTOR        10 /* 0xFFEA ADC */
#define USCIAB0TX_VECTOR    12 /* 0xFFEC USCI A0/B0 Transmit */
#define USCIAB0RX_VECTOR    14 /* 0xFFEE USCI A0/B0 Receive */
#define TIMERA1_VECTOR      16 /* 0xFFF0 Timer A CC1-2, TA */
#define TIMERA0_VECTOR      18 /* 0xFFF2 Timer A CC0 */
#define WDT_VECTOR          20 /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR  22 /* 0xFFF6 Comparator A */
#define TIMERB1_VECTOR      24 /* 0xFFF8 Timer B CC1-6, TB */
#define TIMERB0_VECTOR      26 /* 0xFFFA Timer B CC0 */
#define NMI_VECTOR          28 /* 0xFFFC Non-maskable */

#define ADC_VECTOR          ADC12_VECTOR /* alias */

#define BSLSKEY_ 0xFFDE         /* The address is used as bootstrap loader security key */
#define BSLSKEY_DISABLE  0xAA55 /* Disables the BSL completely */
#define BSLSKEY_NO_ERASE 0x0000 /* Disables the erasure of the flash if an invalid password is supplied */


#endif /* #ifndef __msp430x22x2 */

Index: msp430x23x0.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430x23x0.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -w -d -r1.1 -r1.2
--- msp430x23x0.h	11 Jul 2007 18:04:34 -0000	1.1
+++ msp430x23x0.h	18 Jun 2008 00:04:40 -0000	1.2
@@ -4,7 +4,7 @@
 /* msp430x23x0.h
  *
  * mspgcc project: MSP430 device headers
- * MSP430x22x2 family header
+ * MSP430x23x0 family header
  *
  * (c) 2007 by Steve Underwood <[email protected]>
  * Originally based in part on work by Texas Instruments Inc.

Index: msp430x24x.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430x24x.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -w -d -r1.4 -r1.5
--- msp430x24x.h	26 May 2008 20:27:52 -0000	1.4
+++ msp430x24x.h	18 Jun 2008 00:04:40 -0000	1.5
@@ -141,39 +141,26 @@
 
 #endif /* #ifndef __DisableCalData */
 
-#define RESERVED0_VECTOR    (0 * 2u)  /* 0xFFC0 Reserved Int. Vector 0 */
-#define RESERVED1_VECTOR    (1 * 2u)  /* 0xFFC2 Reserved Int. Vector 1 */
-#define RESERVED2_VECTOR    (2 * 2u)  /* 0xFFC4 Reserved Int. Vector 2 */
-#define RESERVED3_VECTOR    (3 * 2u)  /* 0xFFC6 Reserved Int. Vector 3 */
-#define RESERVED4_VECTOR    (4 * 2u)  /* 0xFFC8 Reserved Int. Vector 4 */
-#define RESERVED5_VECTOR    (5 * 2u)  /* 0xFFCA Reserved Int. Vector 5 */
-#define RESERVED6_VECTOR    (6 * 2u)  /* 0xFFCC Reserved Int. Vector 6 */
-#define RESERVED7_VECTOR    (7 * 2u)  /* 0xFFCE Reserved Int. Vector 7 */
-#define RESERVED8_VECTOR    (8 * 2u)  /* 0xFFD0 Reserved Int. Vector 8 */
-#define RESERVED9_VECTOR    (9 * 2u)  /* 0xFFD2 Reserved Int. Vector 9 */
-#define RESERVED10_VECTOR   (10 * 2u) /* 0xFFD4 Reserved Int. Vector 10 */
-#define RESERVED11_VECTOR   (11 * 2u) /* 0xFFD6 Reserved Int. Vector 11 */
-#define RESERVED12_VECTOR   (12 * 2u) /* 0xFFD8 Reserved Int. Vector 12 */
-#define RESERVED13_VECTOR   (13 * 2u) /* 0xFFDA Reserved Int. Vector 13 */
-#define RESERVED14_VECTOR   (14 * 2u) /* 0xFFDC Reserved Int. Vector 14 */
-#define RESERVED15_VECTOR   (15 * 2u) /* 0xFFDE Reserved Int. Vector 15 */
-#define USCIAB1TX_VECTOR    (16 * 2u) /* 0xFFE0 USCI A1/B1 Transmit */
-#define USCIAB1RX_VECTOR    (17 * 2u) /* 0xFFE2 USCI A1/B1 Receive */
-#define PORT1_VECTOR        (18 * 2u) /* 0xFFE4 Port 1 */
-#define PORT2_VECTOR        (19 * 2u) /* 0xFFE6 Port 2 */
-#define RESERVED20_VECTOR   (20 * 2u) /* 0xFFE8 Reserved Int. Vector 20 */
-#define ADC12_VECTOR        (21 * 2u) /* 0xFFEA ADC */
-#define USCIAB0TX_VECTOR    (22 * 2u) /* 0xFFEC USCI A0/B0 Transmit */
-#define USCIAB0RX_VECTOR    (23 * 2u) /* 0xFFEE USCI A0/B0 Receive */
-#define TIMERA1_VECTOR      (24 * 2u) /* 0xFFF0 Timer A CC1-2, TA */
-#define TIMERA0_VECTOR      (25 * 2u) /* 0xFFF2 Timer A CC0 */
-#define WDT_VECTOR          (26 * 2u) /* 0xFFF4 Watchdog Timer */
-#define COMPARATORA_VECTOR  (27 * 2u) /* 0xFFF6 Comparator A */
-#define TIMERB1_VECTOR      (28 * 2u) /* 0xFFF8 Timer B CC1-6, TB */
-#define TIMERB0_VECTOR      (29 * 2u) /* 0xFFFA Timer B CC0 */
-#define NMI_VECTOR          (30 * 2u) /* 0xFFFC Non-maskable */
+#define USCIAB1TX_VECTOR    0  /* 0xFFE0 USCI A1/B1 Transmit */
+#define USCIAB1RX_VECTOR    2  /* 0xFFE2 USCI A1/B1 Receive */
+#define PORT1_VECTOR        4  /* 0xFFE4 Port 1 */
+#define PORT2_VECTOR        6  /* 0xFFE6 Port 2 */
+#define RESERVED20_VECTOR   8  /* 0xFFE8 Reserved Int. Vector 20 */
+#define ADC12_VECTOR        10 /* 0xFFEA ADC */
+#define USCIAB0TX_VECTOR    12 /* 0xFFEC USCI A0/B0 Transmit */
+#define USCIAB0RX_VECTOR    14 /* 0xFFEE USCI A0/B0 Receive */
+#define TIMERA1_VECTOR      16 /* 0xFFF0 Timer A CC1-2, TA */
+#define TIMERA0_VECTOR      18 /* 0xFFF2 Timer A CC0 */
+#define WDT_VECTOR          20 /* 0xFFF4 Watchdog Timer */
+#define COMPARATORA_VECTOR  22 /* 0xFFF6 Comparator A */
+#define TIMERB1_VECTOR      24 /* 0xFFF8 Timer B CC1-6, TB */
+#define TIMERB0_VECTOR      26 /* 0xFFFA Timer B CC0 */
+#define NMI_VECTOR          28 /* 0xFFFC Non-maskable */
 
+#define ADC_VECTOR          ADC12_VECTOR /* alias */
 
-#define ADC_VECTOR          ADC12_VECTOR
+#define BSLSKEY_ 0xFFDE         /* The address is used as bootstrap loader security key */
+#define BSLSKEY_DISABLE  0xAA55 /* Disables the BSL completely */
+#define BSLSKEY_NO_ERASE 0x0000 /* Disables the erasure of the flash if an invalid password is supplied */
 
 #endif /* #ifndef __msp430x24x */

Index: msp430x24x1.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430x24x1.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -w -d -r1.4 -r1.5
--- msp430x24x1.h	26 May 2008 20:27:52 -0000	1.4
+++ msp430x24x1.h	18 Jun 2008 00:04:40 -0000	1.5
@@ -1,10 +1,10 @@
 #ifndef __msp430x24x1
 #define __msp430x24x1
 
-/* msp430x24x.h
+/* msp430x24x1.h
  *
  * mspgcc project: MSP430 device headers
- * MSP430x14x family header
+ * MSP430x24x family header
  *
  * (c) 2007 by Steve Underwood <[email protected]>
  * Originally based in part on work by Texas Instruments Inc.
@@ -126,36 +126,24 @@
 
 #endif /* #ifndef __DisableCalData */
 
-#define RESERVED0_VECTOR    (0 * 2u)  /* 0xFFC0 Reserved Int. Vector 0 */
-#define RESERVED1_VECTOR    (1 * 2u)  /* 0xFFC2 Reserved Int. Vector 1 */
-#define RESERVED2_VECTOR    (2 * 2u)  /* 0xFFC4 Reserved Int. Vector 2 */
-#define RESERVED3_VECTOR    (3 * 2u)  /* 0xFFC6 Reserved Int. Vector 3 */
-#define RESERVED4_VECTOR    (4 * 2u)  /* 0xFFC8 Reserved Int. Vector 4 */
-#define RESERVED5_VECTOR    (5 * 2u)  /* 0xFFCA Reserved Int. Vector 5 */
-#define RESERVED6_VECTOR    (6 * 2u)  /* 0xFFCC Reserved Int. Vector 6 */
-#define RESERVED7_VECTOR    (7 * 2u)  /* 0xFFCE Reserved Int. Vector 7 */
-#define RESERVED8_VECTOR    (8 * 2u)  /* 0xFFD0 Reserved Int. Vector 8 */
-#define RESERVED9_VECTOR    (9 * 2u)  /* 0xFFD2 Reserved Int. Vector 9 */
-#define RESERVED10_VECTOR   (10 * 2u) /* 0xFFD4 Reserved Int. Vector 10 */
-#define RESERVED11_VECTOR   (11 * 2u) /* 0xFFD6 Reserved Int. Vector 11 */
-#define RESERVED12_VECTOR   (12 * 2u) /* 0xFFD8 Reserved Int. Vector 12 */
-#define RESERVED13_VECTOR   (13 * 2u) /* 0xFFDA Reserved Int. Vector 13 */
-#define RESERVED14_VECTOR   (14 * 2u) /* 0xFFDC Reserved Int. Vector 14 */
-#define RESERVED15_VECTOR   (15 * 2u) /* 0xFFDE Reserved Int. Vector 15 */
-#define USCIAB1TX_VECTOR    (16 * 2u) /* 0xFFE0 USCI A1/B1 Transmit */
-#define USCIAB1RX_VECTOR    (17 * 2u) /* 0xFFE2 USCI A1/B1 Receive */
-#define PORT1_VECTOR        (18 * 2u) /* 0xFFE4 Port 1 */
-#define PORT2_VECTOR        (19 * 2u) /* 0xFFE6 Port 2 */
-#define RESERVED20_VECTOR   (20 * 2u) /* 0xFFE8 Reserved Int. Vector 20 */
-#define RESERVED21_VECTOR   (21 * 2u) /* 0xFFEA Reserved Int. Vector 21 */
-#define USCIAB0TX_VECTOR    (22 * 2u) /* 0xFFEC USCI A0/B0 Transmit */
-#define USCIAB0RX_VECTOR    (23 * 2u) /* 0xFFEE USCI A0/B0 Receive */
-#define TIMERA1_VECTOR      (24 * 2u) /* 0xFFF0 Timer A CC1-2, TA */
-#define TIMERA0_VECTOR      (25 * 2u) /* 0xFFF2 Timer A CC0 */
-#define WDT_VECTOR          (26 * 2u) /* 0xFFF4 Watchdog Timer */
-#define COMPARATORA_VECTOR  (27 * 2u) /* 0xFFF6 Comparator A */
-#define TIMERB1_VECTOR      (28 * 2u) /* 0xFFF8 Timer B CC1-6, TB */
-#define TIMERB0_VECTOR      (29 * 2u) /* 0xFFFA Timer B CC0 */
-#define NMI_VECTOR          (30 * 2u) /* 0xFFFC Non-maskable */
+#define USCIAB1TX_VECTOR    0  /* 0xFFE0 USCI A1/B1 Transmit */
+#define USCIAB1RX_VECTOR    2  /* 0xFFE2 USCI A1/B1 Receive */
+#define PORT1_VECTOR        4  /* 0xFFE4 Port 1 */
+#define PORT2_VECTOR        6  /* 0xFFE6 Port 2 */
+#define RESERVED20_VECTOR   8  /* 0xFFE8 Reserved Int. Vector 20 */
+#define RESERVED21_VECTOR   10 /* 0xFFEA Reserved Int. Vector 21 */
+#define USCIAB0TX_VECTOR    12 /* 0xFFEC USCI A0/B0 Transmit */
+#define USCIAB0RX_VECTOR    14 /* 0xFFEE USCI A0/B0 Receive */
+#define TIMERA1_VECTOR      16 /* 0xFFF0 Timer A CC1-2, TA */
+#define TIMERA0_VECTOR      18 /* 0xFFF2 Timer A CC0 */
+#define WDT_VECTOR          20 /* 0xFFF4 Watchdog Timer */
+#define COMPARATORA_VECTOR  22 /* 0xFFF6 Comparator A */
+#define TIMERB1_VECTOR      24 /* 0xFFF8 Timer B CC1-6, TB */
+#define TIMERB0_VECTOR      26 /* 0xFFFA Timer B CC0 */
+#define NMI_VECTOR          28 /* 0xFFFC Non-maskable */
+
+#define BSLSKEY_ 0xFFDE         /* The address is used as bootstrap loader security key */
+#define BSLSKEY_DISABLE  0xAA55 /* Disables the BSL completely */
+#define BSLSKEY_NO_ERASE 0x0000 /* Disables the erasure of the flash if an invalid password is supplied */
 
 #endif /* #ifndef __msp430x24x1 */


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