CVS: packaging/patches binutils-2.18-430X.patch, 1.1, 1.2 gdb-6.8-430X.patch, 1.1, 1.2
"Sergey A. Borshch" <[email protected]> Wed, 17 Sep 2008 02:51:02 -0700
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/packaging/patches
In directory sc8-pr-cvs16.sourceforge.net:/tmp/cvs-serv29224/patches
Modified Files:
binutils-2.18-430X.patch gdb-6.8-430X.patch
Log Message:
objdump & gdb crash on disassembling 430X double-operand instructions with #N as dst fixed
Index: binutils-2.18-430X.patch
===================================================================
RCS file: /cvsroot/mspgcc/packaging/patches/binutils-2.18-430X.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -w -d -r1.1 -r1.2
--- binutils-2.18-430X.patch 15 Sep 2008 10:13:14 -0000 1.1
+++ binutils-2.18-430X.patch 17 Sep 2008 09:50:57 -0000 1.2
@@ -5208,7 +5208,7 @@
{
/* Special case: rla and rlc are the only 2 emulated instructions that
fall into two operand instructions. */
-@@ -319,348 +312,341 @@
+@@ -319,348 +312,352 @@
if (regd != regs || as != ad)
return 0; /* May be 'data' section. */
@@ -5465,7 +5465,7 @@
+ return -1;
+ }
+
-+ /* extract repeat count if any */
++ // extract repeat count if any
+ if ( am == 0 ) // extension word for register mode
+ {
+ if (insn & 0x008f) // repetitions
@@ -5477,7 +5477,7 @@
+ }
+ }
+
-+ /* extract operands */
++ // extract operands
+ dst = msp430dis_operand(addr + cmd_len, info, reg, am, &cmd_len) | ((insn & 0x0000000f) << 16);
+ dst = (dst << 12) >> 12; // sign extension
+ msp430x_decode_operand(reg, am, addr + cmd_len, dst, OP_20BIT, op, comm);
@@ -5613,13 +5613,16 @@
+
+ if (ad == 0 && regd == 3)
+ {
-+ /* R3 is illegal as dest: may be data section. */
++ // R3 is illegal as dest: may be data section.
++ if (comm1)
+ strcpy (comm1, _("Illegal as 2-op instr"));
++ else if (comm2)
++ strcpy (comm2, _("Illegal as 2-op instr"));
+ return -1;
}
+ *op_width = msp430x_opwidth(insn);
+
-+ /* extract repeat count if any */
++ // extract repeat count if any
+ if ( as == 0 && ad == 0 ) // extension word for register mode
+ {
+ if (insn & 0x008f) // repetitions
@@ -5630,7 +5633,7 @@
+ *repeats = 0 - (insn & 0xf); // negative number is #N
+ }
+ }
-+ /* extract operands */
++ // extract operands
+ ops = msp430dis_operand(addr + cmd_len, info, regs, as, &cmd_len) | ((insn & 0x00000780) << 9);
+ ops = (ops << 12) >> 12; // sign extension
+ msp430x_decode_operand(regs, as, addr + cmd_len, ops, OP_20BIT, op1, comm1);
@@ -5667,69 +5670,10 @@
- regs = (insn & 0x0f00) >> 8;
- as = (insn & 0x0030) >> 4;
- ad = (insn & 0x0080) >> 7;
-+ int dst = 0;
-+ typedef struct
-+ {
-+ int as, regs;
-+ int ad, regd;
-+ int length;
-+ }
-+ operands_t;
-+
-+ static operands_t const operands_table[] =
-+ {
-+ { 2, -1, 0, -1, 0 }, // 0 @Rsrc, Rdst
-+ { 3, -1, 0, -1, 0 }, // 1 @Rsrc+, Rdst
-+ { 1, 2, 0, -1, 2 }, // 2 &abs20, Rdst
-+ { 1, -1, 0, -1, 2 }, // 3 x(Rsrc), Rdst
-+ { 0, 0, 0, 0, 0 }, // 4
-+ { 0, 0, 0, 0, 0 }, // 5
-+ { 0, -1, 1, 2, 2 }, // 6 Rsrc, &abs20
-+ { 0, -1, 1, -1, 2 }, // 7 Rsrc, x(Rdst)
-+ { 3, 0, 0, -1, 2 }, // 8 #imm20, Rdst
-+ { 3, 0, 0, -1, 2 }, // 9 #imm20, Rdst
-+ { 3, 0, 0, -1, 2 }, // a #imm20, Rdst
-+ { 3, 0, 0, -1, 2 }, // b #imm20, Rdst
-+ { 0, -1, 0, -1, 0 }, // c Rsrc, Rdst
-+ { 0, -1, 0, -1, 0 }, // d Rsrc, Rdst
-+ { 0, -1, 0, -1, 0 }, // e Rsrc, Rdst
-+ { 0, -1, 0, -1, 0 }, // f Rsrc, Rdst
-+ };
-+
-+ operands_t operands = operands_table[(insn >> 4) & 0xf];
-+ if(((insn >> 4) & 0xf) == 6)
-+ dst = msp430dis_opcode (addr + cmd_len, info) | ((insn & 0x000f) << 16);
-+ else if(((insn >> 4) & 0xb) == 3)
-+ dst = (short)msp430dis_opcode (addr + cmd_len, info);
-+ else if(operands.length != 0)
-+ dst = msp430dis_opcode(addr + cmd_len, info) | ((insn & 0x0f00) << 8);
-+
-+ if(operands.regs == -1)
-+ operands.regs = (insn >> 8 ) & 0x000f;
-+ if(operands.regd == -1)
-+ operands.regd = (insn >> 0 ) & 0x000f;
-+
-+ /* extract operands */
-+ msp430x_decode_operand(operands.regs, operands.as, addr + cmd_len, dst,
-+ ((insn >> 4) & 0xf) == 3 ? OP_16BIT_HEX : OP_20BIT_HEX, op1, comm1);
-+ msp430x_decode_operand(operands.regd, operands.ad, addr + cmd_len, dst,
-+ ((insn >> 4) & 0xf) == 7 ? OP_16BIT_HEX : OP_20BIT_HEX, op2, comm2);
-+ return cmd_len + operands.length;
-+}
-
+-
- if (regd != 0) /* Destination register is not a PC. */
- return 0;
-+static int
-+msp430x_emulated (disassemble_info *info,
-+ struct msp430_opcode_s const *opcode,
-+ bfd_vma addr,
-+ unsigned int insn,
-+ char *op1,
-+ char *comm1,
-+ opwidth_t *op_width,
-+ int *repeats)
-+{
-
+-
- /* dst is a source register. */
- if (as == 0)
- {
@@ -5748,7 +5692,9 @@
- }
- }
- else if (as == 2)
-- {
++ int dst = 0;
++ typedef struct
+ {
- if (regs == 2)
- {
- *cycles = 2;
@@ -5795,12 +5741,65 @@
- *cycles = 2;
- sprintf (op1, "@r%d+", regs);
- }
-- }
++ int as, regs;
++ int ad, regd;
++ int length;
++ }
++ operands_t;
++
++ static operands_t const operands_table[] =
++ {
++ { 2, -1, 0, -1, 0 }, // 0 @Rsrc, Rdst
++ { 3, -1, 0, -1, 0 }, // 1 @Rsrc+, Rdst
++ { 1, 2, 0, -1, 2 }, // 2 &abs20, Rdst
++ { 1, -1, 0, -1, 2 }, // 3 x(Rsrc), Rdst
++ { 0, 0, 0, 0, 0 }, // 4
++ { 0, 0, 0, 0, 0 }, // 5
++ { 0, -1, 1, 2, 2 }, // 6 Rsrc, &abs20
++ { 0, -1, 1, -1, 2 }, // 7 Rsrc, x(Rdst)
++ { 3, 0, 0, -1, 2 }, // 8 #imm20, Rdst
++ { 3, 0, 0, -1, 2 }, // 9 #imm20, Rdst
++ { 3, 0, 0, -1, 2 }, // a #imm20, Rdst
++ { 3, 0, 0, -1, 2 }, // b #imm20, Rdst
++ { 0, -1, 0, -1, 0 }, // c Rsrc, Rdst
++ { 0, -1, 0, -1, 0 }, // d Rsrc, Rdst
++ { 0, -1, 0, -1, 0 }, // e Rsrc, Rdst
++ { 0, -1, 0, -1, 0 }, // f Rsrc, Rdst
++ };
++
++ operands_t operands = operands_table[(insn >> 4) & 0xf];
++ if(((insn >> 4) & 0xf) == 6)
++ dst = msp430dis_opcode (addr + cmd_len, info) | ((insn & 0x000f) << 16);
++ else if(((insn >> 4) & 0xb) == 3)
++ dst = (short)msp430dis_opcode (addr + cmd_len, info);
++ else if(operands.length != 0)
++ dst = msp430dis_opcode(addr + cmd_len, info) | ((insn & 0x0f00) << 8);
++
++ if(operands.regs == -1)
++ operands.regs = (insn >> 8 ) & 0x000f;
++ if(operands.regd == -1)
++ operands.regd = (insn >> 0 ) & 0x000f;
++
++ if (operands.regd == 3)
++ {
++ // R3 is illegal as dest: may be data section.
++ if (comm1)
++ strcpy (comm1, _("Illegal as address instr"));
++ else if (comm2)
++ strcpy (comm2, _("Illegal as address instr"));
++ return -1;
+ }
- else if (as == 1)
-+ switch(opcode_variant(opcode))
- {
+- {
- * cycles = 3;
--
++ // extract operands
++ msp430x_decode_operand(operands.regs, operands.as, addr + cmd_len, dst,
++ ((insn >> 4) & 0xf) == 3 ? OP_16BIT_HEX : OP_20BIT_HEX, op1, comm1);
++ msp430x_decode_operand(operands.regd, operands.ad, addr + cmd_len, dst,
++ ((insn >> 4) & 0xf) == 7 ? OP_16BIT_HEX : OP_20BIT_HEX, op2, comm2);
++ return cmd_len + operands.length;
++}
+
- if (regs == 0)
- {
- /* PC relative. */
@@ -5831,14 +5830,28 @@
- cmd_len += 2;
- sprintf (op1, "%d(r%d)", dst, regs);
- }
+- }
++static int
++msp430x_emulated (disassemble_info *info,
++ struct msp430_opcode_s const *opcode,
++ bfd_vma addr,
++ unsigned int insn,
++ char *op1,
++ char *comm1,
++ opwidth_t *op_width,
++ int *repeats)
++{
+
+- return cmd_len;
++ switch(opcode_variant(opcode))
++ {
+ case V_NONE:
+ case V_X_SHIFT:
-+ /* emulated by double operand instruction */
++ // emulated by double operand instruction
+ return msp430x_doubleoperand(info, opcode, addr, insn, (char *)0, op1,
+ (char *)0, comm1, op_width, repeats);
+ case V_RETA: // reta, substituted by mova
-+ return msp430x_address(info, addr, insn, (char *)0, (char *)0,
-+ (char *)0, (char *)0);
++ return 2;
+ case V_EMU_ADDR: // substituted by other address instruction
+ return msp430x_address(info, addr, insn, (char *)0, op1,
+ (char *)0, comm1);
@@ -5847,14 +5860,12 @@
+ comm1, (char *)0);
+ default:
+ break;
- }
--
-- return cmd_len;
++ }
+ return 0;
}
int
-@@ -668,81 +654,135 @@
+@@ -668,89 +665,147 @@
{
void *stream = info->stream;
fprintf_ftype prin = info->fprintf_func;
@@ -5936,6 +5947,29 @@
if (cmd_len)
break;
}
+-
+- switch (opcode->insn_opnumb)
+- {
+- case 0:
+- cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
+- break;
+- case 2:
+- cmd_len =
+- msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
+- comm1, comm2, &cycles);
+- if (insn & BYTE_OPERATION)
+- bc = ".b";
+- break;
+- case 1:
+- cmd_len =
+- msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
+- &cycles);
+- if (insn & BYTE_OPERATION && opcode->fmt != 3)
+- bc = ".b";
+- break;
+- default:
+- break;
+- }
+ if(opcode_format(opcode) < FMT_X)
+ switch (opcode->insn_opnumb)
+ {
@@ -5974,17 +6008,14 @@
+ cmd_len = msp430x_singleoperand (info, opcode, addr, insn, op1, comm1,
+ &repeats);
+ break;
-+
+ case FMT_X_EXCEPTION:
+ cmd_len = msp430x_exception (info, opcode, addr, insn, op1, op2,
+ comm1, comm2, &op_width);
+ break;
-+
+ case FMT_X_DOUBLE_OPERAND:
+ cmd_len = msp430x_doubleoperand (info, opcode, addr, insn, op1, op2,
+ comm1, comm2, &op_width, &repeats);
+ break;
-+
+ case FMT_X_EMULATED:
+ cmd_len = msp430x_emulated (info, opcode, addr, insn, op1,
+ comm1, &op_width, &repeats);
@@ -5994,33 +6025,9 @@
+ cmd_len = msp430x_address (info, addr, insn, op1, op2,
+ comm1, comm2);
+ break;
-+
+ default:
+ break;
+ }
-
-- switch (opcode->insn_opnumb)
-- {
-- case 0:
-- cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
-- break;
-- case 2:
-- cmd_len =
-- msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
-- comm1, comm2, &cycles);
-- if (insn & BYTE_OPERATION)
-- bc = ".b";
-- break;
-- case 1:
-- cmd_len =
-- msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
-- &cycles);
-- if (insn & BYTE_OPERATION && opcode->fmt != 3)
-- bc = ".b";
-- break;
-- default:
-- break;
-- }
}
if (cmd_len)
@@ -6032,7 +6039,8 @@
if (cmd_len < 1)
{
/* Unknown opcode, or invalid combination of operands. */
-@@ -750,7 +790,16 @@
+- (*prin) (stream, ".word 0x%04x; ????", PS (insn));
++ (*prin) (stream, ".word 0x%04x; ????\t%s%s", PS (insn), comm1, comm2);
return 2;
}
@@ -6050,7 +6058,7 @@
if (*op1)
(*prin) (stream, "\t%s", op1);
-@@ -769,23 +818,11 @@
+@@ -769,23 +824,11 @@
if (*comm1 || *comm2)
(*prin) (stream, ";");
Index: gdb-6.8-430X.patch
===================================================================
RCS file: /cvsroot/mspgcc/packaging/patches/gdb-6.8-430X.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -w -d -r1.1 -r1.2
--- gdb-6.8-430X.patch 15 Sep 2008 10:13:14 -0000 1.1
+++ gdb-6.8-430X.patch 17 Sep 2008 09:50:57 -0000 1.2
@@ -1646,7 +1646,7 @@
{
/* Special case: rla and rlc are the only 2 emulated instructions that
fall into two operand instructions. */
-@@ -319,348 +312,341 @@
+@@ -319,348 +312,352 @@
if (regd != regs || as != ad)
return 0; /* May be 'data' section. */
@@ -1903,7 +1903,7 @@
+ return -1;
+ }
+
-+ /* extract repeat count if any */
++ // extract repeat count if any
+ if ( am == 0 ) // extension word for register mode
+ {
+ if (insn & 0x008f) // repetitions
@@ -1915,7 +1915,7 @@
+ }
+ }
+
-+ /* extract operands */
++ // extract operands
+ dst = msp430dis_operand(addr + cmd_len, info, reg, am, &cmd_len) | ((insn & 0x0000000f) << 16);
+ dst = (dst << 12) >> 12; // sign extension
+ msp430x_decode_operand(reg, am, addr + cmd_len, dst, OP_20BIT, op, comm);
@@ -2051,13 +2051,16 @@
+
+ if (ad == 0 && regd == 3)
+ {
-+ /* R3 is illegal as dest: may be data section. */
++ // R3 is illegal as dest: may be data section.
++ if (comm1)
+ strcpy (comm1, _("Illegal as 2-op instr"));
++ else if (comm2)
++ strcpy (comm2, _("Illegal as 2-op instr"));
+ return -1;
}
+ *op_width = msp430x_opwidth(insn);
+
-+ /* extract repeat count if any */
++ // extract repeat count if any
+ if ( as == 0 && ad == 0 ) // extension word for register mode
+ {
+ if (insn & 0x008f) // repetitions
@@ -2068,7 +2071,7 @@
+ *repeats = 0 - (insn & 0xf); // negative number is #N
+ }
+ }
-+ /* extract operands */
++ // extract operands
+ ops = msp430dis_operand(addr + cmd_len, info, regs, as, &cmd_len) | ((insn & 0x00000780) << 9);
+ ops = (ops << 12) >> 12; // sign extension
+ msp430x_decode_operand(regs, as, addr + cmd_len, ops, OP_20BIT, op1, comm1);
@@ -2105,69 +2108,10 @@
- regs = (insn & 0x0f00) >> 8;
- as = (insn & 0x0030) >> 4;
- ad = (insn & 0x0080) >> 7;
-+ int dst = 0;
-+ typedef struct
-+ {
-+ int as, regs;
-+ int ad, regd;
-+ int length;
-+ }
-+ operands_t;
-+
-+ static operands_t const operands_table[] =
-+ {
-+ { 2, -1, 0, -1, 0 }, // 0 @Rsrc, Rdst
-+ { 3, -1, 0, -1, 0 }, // 1 @Rsrc+, Rdst
-+ { 1, 2, 0, -1, 2 }, // 2 &abs20, Rdst
-+ { 1, -1, 0, -1, 2 }, // 3 x(Rsrc), Rdst
-+ { 0, 0, 0, 0, 0 }, // 4
-+ { 0, 0, 0, 0, 0 }, // 5
-+ { 0, -1, 1, 2, 2 }, // 6 Rsrc, &abs20
-+ { 0, -1, 1, -1, 2 }, // 7 Rsrc, x(Rdst)
-+ { 3, 0, 0, -1, 2 }, // 8 #imm20, Rdst
-+ { 3, 0, 0, -1, 2 }, // 9 #imm20, Rdst
-+ { 3, 0, 0, -1, 2 }, // a #imm20, Rdst
-+ { 3, 0, 0, -1, 2 }, // b #imm20, Rdst
-+ { 0, -1, 0, -1, 0 }, // c Rsrc, Rdst
-+ { 0, -1, 0, -1, 0 }, // d Rsrc, Rdst
-+ { 0, -1, 0, -1, 0 }, // e Rsrc, Rdst
-+ { 0, -1, 0, -1, 0 }, // f Rsrc, Rdst
-+ };
-+
-+ operands_t operands = operands_table[(insn >> 4) & 0xf];
-+ if(((insn >> 4) & 0xf) == 6)
-+ dst = msp430dis_opcode (addr + cmd_len, info) | ((insn & 0x000f) << 16);
-+ else if(((insn >> 4) & 0xb) == 3)
-+ dst = (short)msp430dis_opcode (addr + cmd_len, info);
-+ else if(operands.length != 0)
-+ dst = msp430dis_opcode(addr + cmd_len, info) | ((insn & 0x0f00) << 8);
-+
-+ if(operands.regs == -1)
-+ operands.regs = (insn >> 8 ) & 0x000f;
-+ if(operands.regd == -1)
-+ operands.regd = (insn >> 0 ) & 0x000f;
-+
-+ /* extract operands */
-+ msp430x_decode_operand(operands.regs, operands.as, addr + cmd_len, dst,
-+ ((insn >> 4) & 0xf) == 3 ? OP_16BIT_HEX : OP_20BIT_HEX, op1, comm1);
-+ msp430x_decode_operand(operands.regd, operands.ad, addr + cmd_len, dst,
-+ ((insn >> 4) & 0xf) == 7 ? OP_16BIT_HEX : OP_20BIT_HEX, op2, comm2);
-+ return cmd_len + operands.length;
-+}
-
+-
- if (regd != 0) /* Destination register is not a PC. */
- return 0;
-+static int
-+msp430x_emulated (disassemble_info *info,
-+ struct msp430_opcode_s const *opcode,
-+ bfd_vma addr,
-+ unsigned int insn,
-+ char *op1,
-+ char *comm1,
-+ opwidth_t *op_width,
-+ int *repeats)
-+{
-
+-
- /* dst is a source register. */
- if (as == 0)
- {
@@ -2186,7 +2130,9 @@
- }
- }
- else if (as == 2)
-- {
++ int dst = 0;
++ typedef struct
+ {
- if (regs == 2)
- {
- *cycles = 2;
@@ -2233,12 +2179,65 @@
- *cycles = 2;
- sprintf (op1, "@r%d+", regs);
- }
-- }
++ int as, regs;
++ int ad, regd;
++ int length;
++ }
++ operands_t;
++
++ static operands_t const operands_table[] =
++ {
++ { 2, -1, 0, -1, 0 }, // 0 @Rsrc, Rdst
++ { 3, -1, 0, -1, 0 }, // 1 @Rsrc+, Rdst
++ { 1, 2, 0, -1, 2 }, // 2 &abs20, Rdst
++ { 1, -1, 0, -1, 2 }, // 3 x(Rsrc), Rdst
++ { 0, 0, 0, 0, 0 }, // 4
++ { 0, 0, 0, 0, 0 }, // 5
++ { 0, -1, 1, 2, 2 }, // 6 Rsrc, &abs20
++ { 0, -1, 1, -1, 2 }, // 7 Rsrc, x(Rdst)
++ { 3, 0, 0, -1, 2 }, // 8 #imm20, Rdst
++ { 3, 0, 0, -1, 2 }, // 9 #imm20, Rdst
++ { 3, 0, 0, -1, 2 }, // a #imm20, Rdst
++ { 3, 0, 0, -1, 2 }, // b #imm20, Rdst
++ { 0, -1, 0, -1, 0 }, // c Rsrc, Rdst
++ { 0, -1, 0, -1, 0 }, // d Rsrc, Rdst
++ { 0, -1, 0, -1, 0 }, // e Rsrc, Rdst
++ { 0, -1, 0, -1, 0 }, // f Rsrc, Rdst
++ };
++
++ operands_t operands = operands_table[(insn >> 4) & 0xf];
++ if(((insn >> 4) & 0xf) == 6)
++ dst = msp430dis_opcode (addr + cmd_len, info) | ((insn & 0x000f) << 16);
++ else if(((insn >> 4) & 0xb) == 3)
++ dst = (short)msp430dis_opcode (addr + cmd_len, info);
++ else if(operands.length != 0)
++ dst = msp430dis_opcode(addr + cmd_len, info) | ((insn & 0x0f00) << 8);
++
++ if(operands.regs == -1)
++ operands.regs = (insn >> 8 ) & 0x000f;
++ if(operands.regd == -1)
++ operands.regd = (insn >> 0 ) & 0x000f;
++
++ if (operands.regd == 3)
++ {
++ // R3 is illegal as dest: may be data section.
++ if (comm1)
++ strcpy (comm1, _("Illegal as address instr"));
++ else if (comm2)
++ strcpy (comm2, _("Illegal as address instr"));
++ return -1;
+ }
- else if (as == 1)
-+ switch(opcode_variant(opcode))
- {
+- {
- * cycles = 3;
--
++ // extract operands
++ msp430x_decode_operand(operands.regs, operands.as, addr + cmd_len, dst,
++ ((insn >> 4) & 0xf) == 3 ? OP_16BIT_HEX : OP_20BIT_HEX, op1, comm1);
++ msp430x_decode_operand(operands.regd, operands.ad, addr + cmd_len, dst,
++ ((insn >> 4) & 0xf) == 7 ? OP_16BIT_HEX : OP_20BIT_HEX, op2, comm2);
++ return cmd_len + operands.length;
++}
+
- if (regs == 0)
- {
- /* PC relative. */
@@ -2269,14 +2268,28 @@
- cmd_len += 2;
- sprintf (op1, "%d(r%d)", dst, regs);
- }
+- }
++static int
++msp430x_emulated (disassemble_info *info,
++ struct msp430_opcode_s const *opcode,
++ bfd_vma addr,
++ unsigned int insn,
++ char *op1,
++ char *comm1,
++ opwidth_t *op_width,
++ int *repeats)
++{
+
+- return cmd_len;
++ switch(opcode_variant(opcode))
++ {
+ case V_NONE:
+ case V_X_SHIFT:
-+ /* emulated by double operand instruction */
++ // emulated by double operand instruction
+ return msp430x_doubleoperand(info, opcode, addr, insn, (char *)0, op1,
+ (char *)0, comm1, op_width, repeats);
+ case V_RETA: // reta, substituted by mova
-+ return msp430x_address(info, addr, insn, (char *)0, (char *)0,
-+ (char *)0, (char *)0);
++ return 2;
+ case V_EMU_ADDR: // substituted by other address instruction
+ return msp430x_address(info, addr, insn, (char *)0, op1,
+ (char *)0, comm1);
@@ -2285,14 +2298,12 @@
+ comm1, (char *)0);
+ default:
+ break;
- }
--
-- return cmd_len;
++ }
+ return 0;
}
int
-@@ -668,77 +654,135 @@
+@@ -668,85 +665,147 @@
{
void *stream = info->stream;
fprintf_ftype prin = info->fprintf_func;
@@ -2370,6 +2381,29 @@
if (cmd_len)
break;
}
+-
+- switch (opcode->insn_opnumb)
+- {
+- case 0:
+- cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
+- break;
+- case 2:
+- cmd_len =
+- msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
+- comm1, comm2, &cycles);
+- if (insn & BYTE_OPERATION)
+- bc = ".b";
+- break;
+- case 1:
+- cmd_len =
+- msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
+- &cycles);
+- if (insn & BYTE_OPERATION && opcode->fmt != 3)
+- bc = ".b";
+- break;
+- default:
+- break;
+- }
+ if(opcode_format(opcode) < FMT_X)
+ switch (opcode->insn_opnumb)
+ {
@@ -2408,17 +2442,14 @@
+ cmd_len = msp430x_singleoperand (info, opcode, addr, insn, op1, comm1,
+ &repeats);
+ break;
-+
+ case FMT_X_EXCEPTION:
+ cmd_len = msp430x_exception (info, opcode, addr, insn, op1, op2,
+ comm1, comm2, &op_width);
+ break;
-+
+ case FMT_X_DOUBLE_OPERAND:
+ cmd_len = msp430x_doubleoperand (info, opcode, addr, insn, op1, op2,
+ comm1, comm2, &op_width, &repeats);
+ break;
-+
+ case FMT_X_EMULATED:
+ cmd_len = msp430x_emulated (info, opcode, addr, insn, op1,
+ comm1, &op_width, &repeats);
@@ -2428,33 +2459,9 @@
+ cmd_len = msp430x_address (info, addr, insn, op1, op2,
+ comm1, comm2);
+ break;
-+
+ default:
+ break;
+ }
-
-- switch (opcode->insn_opnumb)
-- {
-- case 0:
-- cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
-- break;
-- case 2:
-- cmd_len =
-- msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
-- comm1, comm2, &cycles);
-- if (insn & BYTE_OPERATION)
-- bc = ".b";
-- break;
-- case 1:
-- cmd_len =
-- msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
-- &cycles);
-- if (insn & BYTE_OPERATION && opcode->fmt != 3)
-- bc = ".b";
-- break;
-- default:
-- break;
-- }
}
if (cmd_len)
@@ -2466,7 +2473,8 @@
if (cmd_len < 1)
{
/* Unknown opcode, or invalid combination of operands. */
-@@ -746,7 +790,16 @@
+- (*prin) (stream, ".word 0x%04x; ????", PS (insn));
++ (*prin) (stream, ".word 0x%04x; ????\t%s%s", PS (insn), comm1, comm2);
return 2;
}
@@ -2484,7 +2492,7 @@
if (*op1)
(*prin) (stream, "\t%s", op1);
-@@ -765,23 +818,11 @@
+@@ -765,23 +824,11 @@
if (*comm1 || *comm2)
(*prin) (stream, ";");
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