CVS: msp430-libc/include/msp430 tlv.h, NONE, 1.1 adc10.h, 1.8, 1.9 adc12.h, 1.10, 1.11 common.h, 1.5, 1.6 esp430e.h, 1.5, 1.6 iostructures.h, 1.10, 1.11 lcd.h, 1.6, 1.7 lcd_a.h, 1.3, 1.4 scanif.h, 1.2, 1.3 sd16.h, 1.8, 1.9 timera.h, 1.13, 1.14 timerb.h, 1.11, 1.12
"Sergey A. Borshch" <[email protected]> Thu, 9 Oct 2008 15:00:16 +0000
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430-libc/include/msp430
In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv7041/msp430-libc/include/msp430
Modified Files:
adc10.h adc12.h common.h esp430e.h iostructures.h lcd.h
lcd_a.h scanif.h sd16.h timera.h timerb.h
Added Files:
tlv.h
Log Message:
* New cpu added:
- F2112, F2122, F2132
- G4250, G4260, G4270
- E4232, E4242, E4252, E4272
- F4351, F4361, F4371
- F4783, F4784, F4793, F4794
- F5418, F5419, F5435...F5438 (empty header file yet)
* headers added: 21x2, 47xx, 54xx(empty), tlv.h
* headers fixed:
- checking for _GNU_ASSEMBLER_ macro changed to GCC predefined macro __ASSEMBLER__.
Unneeded -D_GNU_ASSEMBLER_ removed from examples and libraries makefiles.
- __msp430_have_sd16a in headers changed to common-style __MSP430_HAS_SD16_A__
- E42x: fixed number of SD16 channels
- F42x0: fixed number of SD16A channels
- G42x0: fixed number of SD16A channels
--- NEW FILE: tlv.h ---
#ifndef __msp430_headers_tlv_h
#define __msp430_headers_tlv_h
/* tlv.h
*
* mspgcc project: MSP430 device headers
* tlv structures
*
* (c) 2008 by Sergey A. Borshch <[email protected]>
*
* $Id: tlv.h,v 1.1 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches: none */
/* TLV Calibration Data Structure */
#define TAG_DCO_30 0x01 /* Tag for DCO30 Calibration Data */
#define TAG_ADC12_1 0x10 /* Tag for ADC12_1 Calibration Data */
#define TAG_EMPTY 0xFE /* Tag for Empty Data Field in Calibration Data */
#define TLV_CHECKSUM_ 0x10C0 /* TLV CHECK SUM */
sfrw(TLV_CHECKSUM, TLV_CHECKSUM_);
#define TLV_DCO_30_TAG_ 0x10F6 /* TLV TAG_DCO30 TAG */
sfrb(TLV_DCO_30_TAG, TLV_DCO_30_TAG_);
#define TLV_DCO_30_LEN_ 0x10F7 /* TLV TAG_DCO30 LEN */
sfrb(TLV_DCO_30_LEN, TLV_DCO_30_LEN_);
#define TLV_ADC12_1_TAG_ 0x10DA /* TLV ADC12_1 TAG */
sfrb(TLV_ADC12_1_TAG, TLV_ADC12_1_TAG_);
#define TLV_ADC12_1_LEN_ 0x10DB /* TLV ADC12_1 LEN */
sfrb(TLV_ADC12_1_LEN, TLV_ADC12_1_LEN_);
#define CAL_ADC_25T85 0x0007 /* Index for 2.5V/85Deg Cal. Value */
#define CAL_ADC_25T30 0x0006 /* Index for 2.5V/30Deg Cal. Value */
#define CAL_ADC_25VREF_FACTOR 0x0005 /* Index for 2.5V Ref. Factor */
#define CAL_ADC_15T85 0x0004 /* Index for 1.5V/85Deg Cal. Value */
#define CAL_ADC_15T30 0x0003 /* Index for 1.5V/30Deg Cal. Value */
#define CAL_ADC_15VREF_FACTOR 0x0002 /* Index for ADC 1.5V Ref. Factor */
#define CAL_ADC_OFFSET 0x0001 /* Index for ADC Offset */
#define CAL_ADC_GAIN_FACTOR 0x0000 /* Index for ADC Gain Factor */
#define CALDCO_16MHZ_ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
#define CALBC1_16MHZ_ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
#define CALDCO_12MHZ_ 0x10FA /* DCOCTL Calibration Data for 12MHz */
sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
#define CALBC1_12MHZ_ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
#define CALDCO_8MHZ_ 0x10FC /* DCOCTL Calibration Data for 8MHz */
sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
#define CALBC1_8MHZ_ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
#define CALDCO_1MHZ_ 0x10FE /* DCOCTL Calibration Data for 1MHz */
sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
#define CALBC1_1MHZ_ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);
#define CAL_DCO_16MHZ 0x0000 /* Index for DCOCTL Calibration Data for 16MHz */
#define CAL_BC1_16MHZ 0x0001 /* Index for BCSCTL1 Calibration Data for 16MHz */
#define CAL_DCO_12MHZ 0x0002 /* Index for DCOCTL Calibration Data for 12MHz */
#define CAL_BC1_12MHZ 0x0003 /* Index for BCSCTL1 Calibration Data for 12MHz */
#define CAL_DCO_8MHZ 0x0004 /* Index for DCOCTL Calibration Data for 8MHz */
#define CAL_BC1_8MHZ 0x0005 /* Index for BCSCTL1 Calibration Data for 8MHz */
#define CAL_DCO_1MHZ 0x0006 /* Index for DCOCTL Calibration Data for 1MHz */
#define CAL_BC1_1MHZ 0x0007 /* Index for BCSCTL1 Calibration Data for 1MHz */
#ifndef __ASSEMBLER__
/* Structured declaration */
typedef enum
{
TAG_DCO_30 = 0x01,
TAG_ADC12_1 = 0x10,
TAG_EMPTY = 0xFE,
} tlv_tags_t;
typedef struct
{
unsigned char tag;
unsigned char length;
struct
{
unsigned char CAL_DCO_16MHZ;
unsigned char CAL_BC1_16MHZ;
unsigned char CAL_DCO_12MHZ;
unsigned char CAL_BC1_12MHZ;
unsigned char CAL_DCO_8MHZ;
unsigned char CAL_BC1_8MHZ;
unsigned char CAL_DCO_1MHZ;
unsigned char CAL_BC1_1MHZ;
} value;
} const dco_30_tag_t;
typedef struct
{
unsigned char tag;
unsigned char length;
struct
{
unsigned int CAL_ADC_GAIN_FACTOR;
unsigned int CAL_ADC_OFFSET;
unsigned int CAL_ADC_15VREF_FACTOR;
unsigned int CAL_ADC_15T30;
unsigned int CAL_ADC_15T85;
unsigned int CAL_ADC_25VREF_FACTOR;
unsigned int CAL_ADC_25T30;
unsigned int CAL_ADC_25T85;
} value;
} const adc12_1_tag_t;
typedef struct
{
unsigned char tag;
unsigned char length;
} const empty_tag_t;
#ifdef __cplusplus
extern "C"
#endif //__cplusplus
struct
{
unsigned int checksum;
empty_tagd_t empty;
unsigned int dummy[11];
adc12_1_tag_t adc12_1;
dco_30_tag_t dco_30;
} const tlv asm("0x10c0");
#endif // __ASSEMBLER__
#endif /* __msp430_headers_tlv_h */
Index: adc10.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/adc10.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -w -d -r1.8 -r1.9
--- adc10.h 22 May 2008 16:01:19 -0000 1.8
+++ adc10.h 9 Oct 2008 15:00:14 -0000 1.9
@@ -39,7 +39,7 @@
#define ADC10SA_ 0x01BC /* ADC10 Data Transfer Start Address */
sfrw(ADC10SA, ADC10SA_);
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
Index: adc12.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/adc12.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -w -d -r1.10 -r1.11
--- adc12.h 12 Jan 2006 00:47:21 -0000 1.10
+++ adc12.h 9 Oct 2008 15:00:14 -0000 1.11
@@ -25,7 +25,7 @@
#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */
sfrw(ADC12IV,ADC12IV_);
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
@@ -91,7 +91,7 @@
#endif
#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
@@ -130,7 +130,7 @@
sfrw(ADC12MEM15,ADC12MEM15_);
#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
Index: common.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/common.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -w -d -r1.5 -r1.6
--- common.h 12 Jan 2006 00:47:21 -0000 1.5
+++ common.h 9 Oct 2008 15:00:14 -0000 1.6
@@ -42,7 +42,7 @@
#define SCG0 0x0040
#define SCG1 0x0080
-#ifdef _GNU_ASSEMBLER_ /* Begin #defines for assembler */
+#ifdef __ASSEMBLER__ /* Begin #defines for assembler */
#define LPM0 CPUOFF
#define LPM1 SCG0+CPUOFF
#define LPM2 SCG1+CPUOFF
Index: esp430e.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/esp430e.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -w -d -r1.5 -r1.6
--- esp430e.h 26 Dec 2006 10:33:14 -0000 1.5
+++ esp430e.h 9 Oct 2008 15:00:14 -0000 1.6
@@ -96,19 +96,28 @@
#define ESP430_STAT1 RET1 /* STATUS1 of ESP430 */
#define WAVEFSV1 RET2 /* Waveform Sample V1 offset corrected*/
#define WAVEFSI1 RET5 /* Waveform Sample I1 offset corrected*/
+#if defined __MSP430_HAS_ESP430E1A__
#define WAVEFSI2 RET6 /* Waveform Sample I2 offset corrected*/
+#endif
#define ACTENERGY1_LO RET8 /* Active energy I1 Low Word */
#define ACTENERGY1_HI RET9 /* Active energy I1 High Word */
+#if defined __MSP430_HAS_ESP430E1A__
#define ACTENERGY2_LO RET10 /* Active energy I2 Low Word */
#define ACTENERGY2_HI RET11 /* Active energy I2 High Word*/
+#endif
#define REACTENERGY_LO RET12 /* Reactive energy Low Word */
#define REACTENERGY_HI RET13 /* Reactive energy High Word */
#define APPENERGY_LO RET14 /* Apparent energy Low Word */
#define APPENERGY_HI RET15 /* Apparent energy High Word */
#define ACTENSPER1_LO RET16 /* Active energy I1 for last mains period Low Word */
#define ACTENSPER1_HI RET17 /* Active energy I1 for last mains period High Word */
+#if defined __MSP430_HAS_ESP430E1A__
#define ACTENSPER2_LO RET18 /* Active energy I2 for last mains period Low Word */
#define ACTENSPER2_HI RET19 /* Active energy I2 for last mains period High Word */
+#elif defined __MSP430_HAS_ESP430E1B__
+#define IRMS_2_LO RET18 /* RMS_2 Low Word */
+#define IRMS_2_HI RET19 /* RMS_2 High Word */
+#endif
#define POWERFCT RET20 /* Power factor */
#define CAPIND RET21 /* Power factor: neg: inductive pos: cap. (LowByte)*/
#define MAINSPERIOD RET22 /* Mains period */
Index: iostructures.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/iostructures.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -w -d -r1.10 -r1.11
--- iostructures.h 11 Apr 2006 08:01:55 -0000 1.10
+++ iostructures.h 9 Oct 2008 15:00:14 -0000 1.11
@@ -1,7 +1,7 @@
/*
* $Id$
*/
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
#ifndef __IOSTRUCTURES_H__
#define __IOSTRUCTURES_H__
@@ -165,5 +165,5 @@
#endif /* __IOSTRUCTURES_H__ */
-#endif /* GNU_ASSEMBLER */
+#endif /* __ASSEMBLER__ */
Index: lcd.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/lcd.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -w -d -r1.6 -r1.7
--- lcd.h 11 Mar 2005 15:49:50 -0000 1.6
+++ lcd.h 9 Oct 2008 15:00:14 -0000 1.7
@@ -61,7 +61,7 @@
#define LCDOGOFF (LCDP2|LCDP1|LCDP0) /* S0 - S39 */
#define LCDMEM_ LCD_BASE+1 /* LCD memory */
-#if defined(_GNU_ASSEMBLER_)
+#if defined(__ASSEMBLER__)
#define LCDMEM LCDMEM_ /* LCD memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */
Index: lcd_a.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/lcd_a.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -w -d -r1.3 -r1.4
--- lcd_a.h 25 Jan 2006 16:39:10 -0000 1.3
+++ lcd_a.h 9 Oct 2008 15:00:14 -0000 1.4
@@ -115,7 +115,7 @@
#define VLCD_3_44 (15<<1) /* VLCD = 3.44V */
#define LCDMEM_ LCD_BASE+1 /* LCD memory */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define LCDMEM LCDMEM_ /* LCD memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */
Index: scanif.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/scanif.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -w -d -r1.2 -r1.3
--- scanif.h 5 Apr 2004 14:05:46 -0000 1.2
+++ scanif.h 9 Oct 2008 15:00:14 -0000 1.3
@@ -48,7 +48,7 @@
sfrw(SIFDACR7, SIFDACR7_);
#define SIFTSM_ 0x01D0 /* SIF, Timing State Machine 0 */
-#ifdef _GNU_ASSEMBLER_
+#ifdef __ASSEMBLER__
#define SIFTSM SIFTSM_ /* SIF, Timing State Machine (for assembler) */
#else
#define SIFTSM ((char*) SIFTSM_) /* SIF, Timing State Machine (for C) */
Index: sd16.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/sd16.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -w -d -r1.8 -r1.9
--- sd16.h 26 Dec 2006 10:33:14 -0000 1.8
+++ sd16.h 9 Oct 2008 15:00:14 -0000 1.9
@@ -14,9 +14,11 @@
/* Switches:
-__msp430_have_sd16a - the SD16 is the "A" type
-__msp430_have_sd16_1
-__msp430_have_sd16_2
+__MSP430_HAS_SD16_A__ - the SD16 is the "A" type
+__MSP430_HAS_SD16_BUF__ - the SD16(_A) has input buffer and SD16AE reg.
+__MSP430_HAS_SD16_CH1__ - the SD16(_A) has channel 1
+__MSP430_HAS_SD16_CH2__ - the SD16(_A) has channel 2
+__MSP430_HAS_SD16_CH3__ - the SD16(_A) has channel 3
*/
#define SD16CTL_ 0x0100 /* Sigma Delta ADC 16 Control Register */
@@ -24,9 +26,11 @@
#define SD16IV_ 0x0110 /* SD16 Interrupt Vector Register */
sfrw(SD16IV, SD16IV_);
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
+#if defined(__MSP430_HAS_SD16_BUF__)
#define SD16AE_ 0x00B7 /* SD16 Analog Input Enable Register */
sfrb(SD16AE, SD16AE_);
+#endif
#else
#define SD16CONF0_ 0x00B7 /* SD16 Internal Configuration Register 0 */
sfrb(SD16CONF0, SD16CONF0_);
@@ -44,7 +48,7 @@
#define SD16MEM0_ 0x0112 /* SD16 Channel 0 Conversion Memory */
sfrw(SD16MEM0, SD16MEM0_);
-#if defined(__msp430_have_sd16_1)
+#if defined(__MSP430_HAS_SD16_CH1__)
#define SD16INCTL1_ 0x00B1 /* SD16 Input Control Register Channel 1 */
sfrb(SD16INCTL1, SD16INCTL1_);
#define SD16PRE1_ 0x00B9 /* SD16 Preload Register Channel 1 */
@@ -55,7 +59,7 @@
sfrw(SD16MEM1, SD16MEM1_);
#endif
-#if defined(__msp430_have_sd16_2)
+#if defined(__MSP430_HAS_SD16_CH2__)
#define SD16INCTL2_ 0x00B2 /* SD16 Input Control Register Channel 2 */
sfrb(SD16INCTL2, SD16INCTL2_);
#define SD16PRE2_ 0x00BA /* SD16 Preload Register Channel 2 */
@@ -66,7 +70,18 @@
sfrw(SD16MEM2, SD16MEM2_);
#endif
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_CH3__)
+#define SD16INCTL3_ 0x00B3 /* SD16 Input Control Register Channel 3 */
+sfrb(SD16INCTL3, SD16INCTL3_);
+#define SD16PRE3_ 0x00BB /* SD16 Preload Register Channel 3 */
+sfrb(SD16PRE3, SD16PRE3_);
+#define SD16CCTL3_ 0x0108 /* SD16 Channel 3 Control Register */
+sfrw(SD16CCTL3, SD16CCTL3_);
+#define SD16MEM3_ 0x0118 /* SD16 Channel 3 Conversion Memory */
+sfrw(SD16MEM3, SD16MEM3_);
+#endif
+
+#if defined(__MSP430_HAS_SD16_A__)
/* SD16AE */
#define SD16AE0 0x0001 /* SD16 External Input Enable 0 */
#define SD16AE1 0x0002 /* SD16 External Input Enable 1 */
@@ -118,7 +133,7 @@
#define SD16DIV0 0x0040 /* SD16 Clock Divider Select 0 */
#define SD16DIV1 0x0080 /* SD16 Clock Divider Select 1 */
#define SD16LP 0x0100 /* SD16 Low Power Mode Enable */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XDIV0 0x0200 /* SD16 2.Clock Divider Select 0 */
#define SD16XDIV1 0x0400 /* SD16 2.Clock Divider Select 1 */
//#define SD16XDIV2 0x0800) /* SD16 2.Clock Divider Select 2 */
@@ -129,7 +144,7 @@
#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
#define SD16DIV_3 (SD16DIV0|SD16DIV1) /* SD16 Clock Divider Select /8 */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XDIV_0 (0x0000) /* SD16 2.Clock Divider Select /1 */
#define SD16XDIV_1 (SD16XDIV0) /* SD16 2.Clock Divider Select /3 */
#define SD16XDIV_2 (SD16XDIV1) /* SD16 2.Clock Divider Select /16 */
@@ -153,7 +168,7 @@
#define SD16OSR0 0x0100 /* SD16 Channel x OverSampling Ratio 0 */
#define SD16OSR1 0x0200 /* SD16 Channel x OverSampling Ratio 1 */
#define SD16SNGL 0x0400 /* SD16 Channel x Single Conversion On/Off */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XOSR 0x0800 /* SD16 Channel x Extended OverSampling Ratio */
#define SD16UNI 0x1000 /* SD16 Channel x Bipolar(0) / Unipolar(1) Mode */
#define SD16BUF0 0x2000 /* SD16 Channel x High Impedance Input Buffer Select: 0 */
@@ -161,7 +176,7 @@
#define SD16BUFG 0x8000 /* SD16 Channel x Buffer Gain 0:Gain=1 / 1:Gain=2 */
#endif
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16OSR_1024 (SD16XOSR|SD16OSR0) /* SD16 Channel x OverSampling Ratio 1024 */
#define SD16OSR_512 (SD16XOSR) /* SD16 Channel x OverSampling Ratio 512 */
#endif
@@ -170,14 +185,14 @@
#define SD16OSR_64 (2<<8) /* SD16 Channel x OverSampling Ratio 64 */
#define SD16OSR_32 (3<<8) /* SD16 Channel x OverSampling Ratio 32 */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16BUF_0 (0<<13) /* SD16 High Imp. Input Buffer: Disabled */
#define SD16BUF_1 (1<<13) /* SD16 High Imp. Input Buffer: Slow */
#define SD16BUF_2 (2<<13) /* SD16 High Imp. Input Buffer: Meduim */
#define SD16BUF_3 (3<<13) /* SD16 High Imp. Input Buffer: Fast */
#endif
-#if !defined(__msp430_have_sd16a)
+#if !defined(__MSP430_HAS_SD16_A__)
#define AFEINCTL0 SD16INCTL0 /* SD16 Input Control Register Channel 0 */
#define AFEINCTL1 SD16INCTL1 /* SD16 Input Control Register Channel 1 */
#define AFEINCTL2 SD16INCTL2 /* SD16 Input Control Register Channel 2 */
@@ -194,7 +209,7 @@
#define SD16DIV_DIV4 SD16DIV_2 /* SD16 Clock Divider Select /4 */
#define SD16DIV_DIV8 SD16DIV_3 /* SD16 Clock Divider Select /8 */
-#if defined(__msp430_have_sd16a)
+#if defined(__MSP430_HAS_SD16_A__)
#define SD16XDIV_DIV1 SD16XDIV_0 /* SD16 2.Clock Divider Select /1 */
#define SD16XDIV_DIV2 SD16XDIV_1 /* SD16 2.Clock Divider Select /3 */
#define SD16XDIV_DIV4 SD16XDIV_2 /* SD16 2.Clock Divider Select /16 */
Index: timera.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timera.h,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -w -d -r1.13 -r1.14
--- timera.h 19 Apr 2006 20:09:52 -0000 1.13
+++ timera.h 9 Oct 2008 15:00:14 -0000 1.14
@@ -16,7 +16,8 @@
__MSP430_HAS_TA2__ - if the device has a timer0 A with 2 channels
__MSP430_HAS_TA3__ - if the device has a timer0 A with 3 channels
-__MSP430_HAS_T1A5__ - if the device has a timer1 A, as well as timer0 A
+__MSP430_HAS_T1A2__ - if the device has a timer1 A with 2 channels, as well as timer0 A
+__MSP430_HAS_T1A5__ - if the device has a timer1 A with 5 channels, as well as timer0 A
*/
@@ -84,7 +85,7 @@
#define CCR2_ TA0CCR2_
#endif
-#if defined(__MSP430_HAS_T1A5__)
+#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__)
#define TA1IV_ 0x011E /* Timer A 1 Interrupt Vector Word */
sfrw (TA1IV, TA1IV_);
#define TA1CTL_ 0x0180 /* Timer A 1 Control */
@@ -93,18 +94,21 @@
sfrw (TA1CCTL0, TA1CCTL0_);
#define TA1CCTL1_ 0x0184 /* Timer A 1 Capture/Compare Control 1 */
sfrw (TA1CCTL1, TA1CCTL1_);
+#if defined(__MSP430_HAS_T1A5__)
#define TA1CCTL2_ 0x0186 /* Timer A 1 Capture/Compare Control 2 */
sfrw (TA1CCTL2, TA1CCTL2_);
#define TA1CCTL3_ 0x0188 /* Timer A 1 Capture/Compare Control 3 */
sfrw (TA1CCTL3, TA1CCTL3_);
#define TA1CCTL4_ 0x018A /* Timer A 1 Capture/Compare Control 4 */
sfrw (TA1CCTL4, TA1CCTL4_);
+#endif
#define TAR1_ 0x0190 /* Timer A 1 */
sfrw (TAR1, TAR1_);
#define TA1CCR0_ 0x0192 /* Timer A 1 Capture/Compare 0 */
sfrw (TA1CCR0, TA1CCR0_);
#define TA1CCR1_ 0x0194 /* Timer A 1 Capture/Compare 1 */
sfrw (TA1CCR1, TA1CCR1_);
+#if defined(__MSP430_HAS_T1A5__)
#define TA1CCR2_ 0x0196 /* Timer A 1 Capture/Compare 2 */
sfrw (TA1CCR2, TA1CCR2_);
#define TA1CCR3_ 0x0198 /* Timer A 1 Capture/Compare 3 */
@@ -112,8 +116,9 @@
#define TA1CCR4_ 0x019A /* Timer A 1 Capture/Compare 4 */
sfrw (TA1CCR4, TA1CCR4_);
#endif
+#endif
-#if !defined(_GNU_ASSEMBLER_)
+#if !defined(__ASSEMBLER__)
/* Structured declaration */
typedef struct {
volatile unsigned
@@ -142,40 +147,54 @@
cm:2;
} __attribute__ ((packed)) tacctl_t;
+#if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__)
/* The timer A declaration itself */
struct timera_t {
tactl_t ctl;
tacctl_t cctl0;
tacctl_t cctl1;
+#if defined(__MSP430_HAS_TA3__)
tacctl_t cctl2;
- volatile unsigned dummy[4]; /* Pad to the next group of registers */
+#else
+ volatile unsigned dummy1[1]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned dummy2[4]; /* Pad to the next group of registers */
volatile unsigned tar;
volatile unsigned taccr0;
volatile unsigned taccr1;
+#if defined(__MSP430_HAS_TA3__)
volatile unsigned taccr2;
+#endif
};
#ifdef __cplusplus
extern "C" struct timera_t timera asm("0x0160");
#else //__cplusplus
struct timera_t timera asm("0x0160");
#endif //__cplusplus
+#endif // __MSP430_HAS_TA2__ || __MSP430_HAS_TA3__
-#if defined(__MSP430_HAS_T1A5__)
+#if defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T1A5__)
/* The timer A1 declaration itself */
struct timera1_t {
tactl_t ctl;
tacctl_t cctl0;
tacctl_t cctl1;
+#if defined(__MSP430_HAS_T1A5__)
tacctl_t cctl2;
tacctl_t cctl3;
tacctl_t cctl4;
- volatile unsigned dummy[2]; /* Pad to the next group of registers */
+#else
+ volatile unsigned dummy1[3]; /* Pad to the next group of registers */
+#endif
+ volatile unsigned dummy2[2]; /* Pad to the next group of registers */
volatile unsigned tar;
volatile unsigned taccr0;
volatile unsigned taccr1;
+#if defined(__MSP430_HAS_T1A5__)
volatile unsigned taccr2;
volatile unsigned taccr3;
volatile unsigned taccr4;
+#endif
};
#ifdef __cplusplus
extern "C" struct timera1_t timera1 asm("0x0180");
Index: timerb.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timerb.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -w -d -r1.11 -r1.12
--- timerb.h 19 Apr 2006 20:09:52 -0000 1.11
+++ timerb.h 9 Oct 2008 15:00:14 -0000 1.12
@@ -59,7 +59,7 @@
#endif
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
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