CVS: python/mspgcc bsl.py, 1.2, 1.2.2.1 memory.py, 1.4, 1.4.2.1

Update of /cvsroot/mspgcc/python/mspgcc
In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv26490/python/mspgcc

Modified Files:
      Tag: MSP430X
	bsl.py memory.py 
Log Message:
add support for ihex reccord "extended segment address" (for images with code/data > 64k)
add support for bsl command to write to extended memory

Index: bsl.py
===================================================================
RCS file: /cvsroot/mspgcc/python/mspgcc/bsl.py,v
retrieving revision 1.2
retrieving revision 1.2.2.1
diff -u -w -d -r1.2 -r1.2.2.1
--- bsl.py	23 Apr 2006 21:37:35 -0000	1.2
+++ bsl.py	19 May 2009 09:07:21 -0000	1.2.2.1
@@ -179,6 +179,7 @@
 #cpu types for "change baudrate"
 #use strings as ID so that they can be used in outputs too
 F1x                     = "F1x family"
+F2x                     = "F2x family"
 F4x                     = "F4x family"
 
 #known device list
@@ -194,6 +195,7 @@
     0xf427: F4x,
     0xf439: F4x,
     0xf449: F4x,
+    0xf26f: F2x,
 }
 
 class BSLException(Exception):
@@ -212,6 +214,7 @@
     BSL_ERASE               = 0x16 #Erase one segment
     BSL_MERAS               = 0x18 #Erase complete FLASH memory
     BSL_CHANGEBAUD          = 0x20 #Change baudrate
+    BSL_SETMEMOFFSET        = 0x21 #MemoryAddress = OffsetValue << 16 + Actual Address
     BSL_LOADPC              = 0x1A #Load PC and start execution
     BSL_TXVERSION           = 0x1E #Get BSL version
 
@@ -277,6 +280,7 @@
         self.protocolMode = self.MODE_BSL
         self.BSLMemAccessWarning = 0            #Default: no warning.
         self.slowmode = 0                       #give a little more time when changing the control lines
+        self.memoffset = 0
 
     def comInit(self, port):
         """Tries to open the serial port given and
@@ -574,15 +578,26 @@
             if (length % 2) != 0:
                 length = length + 1
 
+        if (self.bslVer >= 0x0212) & (cmd == self.BSL_TXBLK) | (cmd == self.BSL_RXBLK):
+            if (self.memoffset!=(addr>>16)):
+                self.memoffset = (addr>>16)
+                self.bslTxRx(self.BSL_SETMEMOFFSET, self.memoffset)
+                if DEBUG > 1: sys.stderr.write("   * bslTxRx(): set mem offset 0x%02x\n" % self.memoffset)
+            addr &= 0xffff	
+        
         #if cmd == self.BSL_TXBLK or cmd == self.BSL_TXPWORD:
         #    length = len + 4
 
         #Add necessary information data to frame
+        if (cmd == self.BSL_SETMEMOFFSET):
+            dataOut =  struct.pack("<HH", length, addr)
+        else:
         dataOut =  struct.pack("<HH", addr, length)
 
         if blkout: #Copy data out of blkout into frame
             dataOut = dataOut + blkout
 
+        if DEBUG > 1: sys.stderr.write("   CMD 0x%04x\n" % cmd)
         self.bslSync(wait)                          #synchronize BSL
         rxFrame = self.comTxRx(cmd, dataOut, len(dataOut))  #Send frame
         if rxFrame:                                 #test answer
@@ -675,7 +690,7 @@
         self.verifyBlk(addr, blkout, action & self.ACTION_ERASE_CHECK)
 
         if action & self.ACTION_PROGRAM:
-            if DEBUG: sys.stderr.write("  Program starting at 0x%04x, %i bytes ...\n" % (addr, len(blkout)))
+            if DEBUG: sys.stderr.write("  Program starting at 0x%05x, %i bytes ...\n" % (addr, len(blkout)))
             self.preparePatch()
             #Program block
             self.bslTxRx(self.BSL_TXBLK, addr, len(blkout), blkout)
@@ -1000,6 +1015,11 @@
             57600:[0x0000, 0x0003],     #nonstandard XXX BSL dummy BCSCTL settings!
            115200:[0x0000, 0x0004],     #nonstandard XXX BSL dummy BCSCTL settings!
         },
+        F2x: {
+             9600:[0x8580, 0x0000],  
+            19200:[0x8b00, 0x0001],
+            38400:[0x8c80, 0x0002],
+        },
         F4x: {
              9600:[0x9800, 0x0000],
             19200:[0xb000, 0x0001],

Index: memory.py
===================================================================
RCS file: /cvsroot/mspgcc/python/mspgcc/memory.py,v
retrieving revision 1.4
retrieving revision 1.4.2.1
diff -u -w -d -r1.4 -r1.4.2.1
--- memory.py	22 May 2008 16:20:02 -0000	1.4
+++ memory.py	19 May 2009 09:07:21 -0000	1.4.2.1
@@ -53,13 +53,14 @@
         segmentdata = []
         currentAddr = 0
         startAddr   = 0
+        extendAddr  = 0
         lines = file.readlines()
         for l in lines:
             if not l.strip(): continue  #skip empty lines
             if l[0] != ':': raise FileFormatError("line not valid intel hex data: '%s...'" % l[0:10])
             l = l.strip()               #fix CR-LF issues...
             length  = int(l[1:3],16)
-            address = int(l[3:7],16)
+            address = int(l[3:7],16) + extendAddr
             type    = int(l[7:9],16)
             check   = int(l[-2:],16)
             if type == 0x00:
@@ -71,7 +72,9 @@
                 for i in range(length):
                     segmentdata.append( chr(int(l[9+2*i:11+2*i],16)) )
                 currentAddr = length + currentAddr
-            elif type in (0x01, 0x02, 0x03, 0x04, 0x05):
+            elif type == 0x02:
+                extendAddr =  int(l[9:13],16) << 4      
+            elif type in (0x01, 0x03, 0x04, 0x05):
                 pass
             else:
                 sys.stderr.write("Ignored unknown field (type 0x%02x) in ihex file.\n" % type)


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