CVS: msp430-libc/include/msp430 timera.h,1.8,1.9

Update of /cvsroot/mspgcc/msp430-libc/include/msp430
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv16078/msp430-libc/include/msp430

Modified Files:
	timera.h 
Log Message:
Fix interrupt definitions for F415 and F417, and bring timer A naming into
line with TI


Index: timera.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timera.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -w -d -r1.8 -r1.9
--- timera.h	31 Mar 2004 21:38:46 -0000	1.8
+++ timera.h	21 Oct 2004 19:41:00 -0000	1.9
@@ -14,42 +14,62 @@
 
 /* Switches: 
 
-__msp430_have_timer1_a5 - if the device has a timer A1, as well as timer A
+__msp430_have_timer1_a5 - if the device has a timer1 A, as well as timer0 A
 
 */
 
-#define TAIV_               0x012E  /* Timer A 0 Interrupt Vector Word */
-sfrw (TAIV,TAIV_);
-#define TACTL_              0x0160  /* Timer A 0 Control */
-sfrw (TACTL,TACTL_);
-#define TACCTL0_            0x0162  /* Timer A 0 Capture/Compare Control 0 */
-sfrw (TACCTL0,TACCTL0_);
-#define TACCTL1_            0x0164  /* Timer A 0 Capture/Compare Control 1 */
-sfrw (TACCTL1,TACCTL1_);
-#define TACCTL2_            0x0166  /* Timer A 0 Capture/Compare Control 2 */
-sfrw (TACCTL2,TACCTL2_);
-#define TAR_                0x0170  /* Timer A 0 */
-sfrw (TAR,TAR_);
-#define TACCR0_             0x0172  /* Timer A 0 Capture/Compare 0 */
-sfrw (TACCR0,TACCR0_);
-#define TACCR1_             0x0174  /* Timer A 0 Capture/Compare 1 */
-sfrw (TACCR1,TACCR1_);
-#define TACCR2_             0x0176  /* Timer A 0 Capture/Compare 2 */
-sfrw (TACCR2,TACCR2_);
+#define TA0IV_              0x012E  /* Timer A 0 Interrupt Vector Word */
+sfrw (TA0IV,TA0IV_);
+#define TA0CTL_             0x0160  /* Timer A 0 Control */
+sfrw (TA0CTL,TA0CTL_);
+#define TA0CCTL0_           0x0162  /* Timer A 0 Capture/Compare Control 0 */
+sfrw (TA0CCTL0,TA0CCTL0_);
+#define TA0CCTL1_           0x0164  /* Timer A 0 Capture/Compare Control 1 */
+sfrw (TA0CCTL1,TA0CCTL1_);
+#define TA0CCTL2_           0x0166  /* Timer A 0 Capture/Compare Control 2 */
+sfrw (TA0CCTL2,TA0CCTL2_);
+#define TA0R_               0x0170  /* Timer A 0 */
+sfrw (TA0R,TA0R_);
+#define TA0CCR0_            0x0172  /* Timer A 0 Capture/Compare 0 */
+sfrw (TA0CCR0,TA0CCR0_);
+#define TA0CCR1_            0x0174  /* Timer A 0 Capture/Compare 1 */
+sfrw (TA0CCR1,TA0CCR1_);
+#define TA0CCR2_            0x0176  /* Timer A 0 Capture/Compare 2 */
+sfrw (TA0CCR2,TA0CCR2_);
 
 /* Alternate register names */
-#define CCTL0_              0x0162  /* Timer A Capture/Compare Control 0 */
-sfrw (CCTL0,CCTL0_);
-#define CCTL1_              0x0164  /* Timer A Capture/Compare Control 1 */
-sfrw (CCTL1,CCTL1_);
-#define CCTL2_              0x0166  /* Timer A Capture/Compare Control 2 */
-sfrw (CCTL2,CCTL2_);
-#define CCR0_               0x0172  /* Timer A Capture/Compare 0 */
-sfrw (CCR0,CCR0_);
-#define CCR1_               0x0174  /* Timer A Capture/Compare 1 */
-sfrw (CCR1,CCR1_);
-#define CCR2_               0x0176  /* Timer A Capture/Compare 2 */
-sfrw (CCR2,CCR2_);
+#define TAIV                TA0IV
+#define TACTL               TA0CTL
+#define TACCTL0             TA0CCTL0
+#define TACCTL1             TA0CCTL1
+#define TACCTL2             TA0CCTL2
+#define TAR                 TA0R
+#define TACCR0              TA0CCR0
+#define TACCR1              TA0CCR1
+#define TACCR2              TA0CCR2
+#define TAIV_               TA0IV_
+#define TACTL_              TA0CTL_
+#define TACCTL0_            TA0CCTL0_
+#define TACCTL1_            TA0CCTL1_
+#define TACCTL2_            TA0CCTL2_
+#define TAR_                TA0R_
+#define TACCR0_             TA0CCR0_
+#define TACCR1_             TA0CCR1_
+#define TACCR2_             TA0CCR2_
+
+/* Further alternate register names */
+#define CCTL0               TA0CCTL0
+#define CCTL1               TA0CCTL1
+#define CCTL2               TA0CCTL2
+#define CCR0                TA0CCR0
+#define CCR1                TA0CCR1
+#define CCR2                TA0CCR2
+#define CCTL0_              TA0CCTL0_
+#define CCTL1_              TA0CCTL1_
+#define CCTL2_              TA0CCTL2_
+#define CCR0_               TA0CCR0_
+#define CCR1_               TA0CCR1_
+#define CCR2_               TA0CCR2_
 
 #if defined(__msp430_have_timer1_a5)
 #define TA1IV_              0x011E  /* Timer A 1 Interrupt Vector Word */
@@ -154,10 +174,10 @@
 #endif
 
 #define TASSEL2             0x0400  /* unused */        /* to distinguish from UART SSELx */
-#define TASSEL1             0x0200  /* Timer A clock source select 0 */
-#define TASSEL0             0x0100  /* Timer A clock source select 1 */
-#define ID1                 0x0080  /* Timer A clock input devider 1 */
-#define ID0                 0x0040  /* Timer A clock input devider 0 */
+#define TASSEL1             0x0200  /* Timer A clock source select 1 */
+#define TASSEL0             0x0100  /* Timer A clock source select 0 */
+#define ID1                 0x0080  /* Timer A clock input divider 1 */
+#define ID0                 0x0040  /* Timer A clock input divider 0 */
 #define MC1                 0x0020  /* Timer A mode control 1 */
 #define MC0                 0x0010  /* Timer A mode control 0 */
 #define TACLR               0x0004  /* Timer A counter clear */



-------------------------------------------------------
This SF.net email is sponsored by: IT Product Guide on ITManagersJournal
Use IT products in your business? Tell us what you think of them. Give us
Your Opinions, Get Free ThinkGeek Gift Certificates! Click to find out more
http://productguide.itmanagersjournal.com/guidepromo.tmpl