CVS: msp430-libc/include/msp430 lcd_a.h,NONE,1.1 basic_clock.h,1.4,1.5 compa.h,1.3,1.4 esp430e.h,1.3,1.4 flash.h,1.3,1.4 lcd.h,1.5,1.6 opamp.h,1.4,1.5 sd16.h,1.3,1.4
Steve Underwood <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430-libc/include/msp430 In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv28330/msp430-libc/include/msp430 Modified Files: basic_clock.h compa.h esp430e.h flash.h lcd.h opamp.h sd16.h Added Files: lcd_a.h Log Message: Additions for 42x 42x0 and 21x1 --- NEW FILE: lcd_a.h --- #if !defined(__msp430_headers_lcd_a_h) #define __msp430_headers_lcd_a_h /* lcd_a.h * * mspgcc project: MSP430 device headers * LCD_A module header * * (c) 2005 by Steve Underwood <[email protected]> * Originally based in part on work by Texas Instruments Inc. * * $Id: lcd_a.h,v 1.1 2005/03/11 15:49:50 coppice Exp $ */ /* Switches: none */ #define LCDACTL_ 0x0090 /* LCD_A Control Register */ sfrb(LCDACTL, LCDACTL_) #define LCDON 0x01 #define LCDSON 0x04 #define LCDMX0 0x08 #define LCDMX1 0x10 #define LCDFREQ0 0x20 #define LCDFREQ1 0x40 #define LCDFREQ2 0x80 /* Display modes coded with Bits 2-4 */ #define LCDSTATIC (LCDSON) #define LCD2MUX (LCDMX0|LCDSON) #define LCD3MUX (LCDMX1|LCDSON) #define LCD4MUX (LCDMX1|LCDMX0|LCDSON) /* Frequency select code with Bits 5-7 */ #define LCDFREQ_32 (0<<5) /* LCD Freq: ACLK divided by 32 */ #define LCDFREQ_64 (1<<5) /* LCD Freq: ACLK divided by 64 */ #define LCDFREQ_96 (2<<5) /* LCD Freq: ACLK divided by 96 */ #define LCDFREQ_128 (3<<5) /* LCD Freq: ACLK divided by 128 */ #define LCDFREQ_192 (4<<5) /* LCD Freq: ACLK divided by 192 */ #define LCDFREQ_256 (5<<5) /* LCD Freq: ACLK divided by 256 */ #define LCDFREQ_384 (6<<5) /* LCD Freq: ACLK divided by 384 */ #define LCDFREQ_512 (7<<5) /* LCD Freq: ACLK divided by 512 */ #define LCDAPCTL0_ 0x00AC /* LCD_A Port Control Register 0 */ sfrb(LCDAPCTL0, LCDAPCTL0_) #define LCDS0 0x01 /* LCD Segment 0 to 3 Enable. */ #define LCDS4 0x02 /* LCD Segment 4 to 7 Enable. */ #define LCDS8 0x04 /* LCD Segment 8 to 11 Enable. */ #define LCDS12 0x08 /* LCD Segment 12 to 15 Enable. */ #define LCDS16 0x10 /* LCD Segment 16 to 19 Enable. */ #define LCDS20 0x20 /* LCD Segment 20 to 23 Enable. */ #define LCDS24 0x40 /* LCD Segment 24 to 27 Enable. */ #define LCDS28 0x80 /* LCD Segment 28 to 31 Enable. */ #define LCDAPCTL1_ 0x00AD /* LCD_A Port Control Register 1 */ sfrb(LCDAPCTL1, LCDAPCTL1_) #define LCDS32 0x01 /* LCD Segment 32 to 35 Enable. */ #define LCDS36 0x02 /* LCD Segment 36 to 39 Enable. */ #define LCDAVCTL0_ 0x00AE /* LCD_A Voltage Control Register 0 */ sfrb(LCDAVCTL0, LCDAVCTL0_) #define LCD2B 0x01 /* Selects 1/2 bias. */ #define VLCDREF0 0x02 /* Selects reference voltage for regulated charge pump: 0 */ #define VLCDREF1 0x04 /* Selects reference voltage for regulated charge pump: 1 */ #define LCDCPEN 0x08 /* LCD Voltage Charge Pump Enable. */ #define VLCDEXT 0x10 /* Select external source for VLCD. */ #define LCDREXT 0x20 /* Selects external connections for LCD mid voltages. */ #define LCDR03EXT 0x40 /* Selects external connection for lowest LCD voltage. */ #define LCDAVCTL1_ 0x00AF /* LCD_A Voltage Control Register 1 */ sfrb(LCDAVCTL1, LCDAVCTL1_) #define VLCD0 0x02 /* VLCD select: 0 */ #define VLCD1 0x04 /* VLCD select: 1 */ #define VLCD2 0x08 /* VLCD select: 2 */ #define VLCD3 0x10 /* VLCD select: 3 */ #define LCDMEM_ LCD_BASE+1 /* LCD memory */ #ifdef _GNU_ASSEMBLER_ #define LCDMEM LCDMEM_ /* LCD memory (for assembler) */ #else #define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */ #endif #define LCDM1_ LCDMEM_ /* LCD memory 1 */ sfrb(LCDM1,LCDM1_); #define LCDM2_ LCD_BASE+0x2 /* LCD memory 2 */ sfrb(LCDM2,LCDM2_); #define LCDM3_ LCD_BASE+0x3 /* LCD memory 3 */ sfrb(LCDM3,LCDM3_); #define LCDM4_ LCD_BASE+0x4 /* LCD memory 4 */ sfrb(LCDM4,LCDM4_); #define LCDM5_ LCD_BASE+0x5 /* LCD memory 5 */ sfrb(LCDM5,LCDM5_); #define LCDM6_ LCD_BASE+0x6 /* LCD memory 6 */ sfrb(LCDM6,LCDM6_); #define LCDM7_ LCD_BASE+0x7 /* LCD memory 7 */ sfrb(LCDM7,LCDM7_); #define LCDM8_ LCD_BASE+0x8 /* LCD memory 8 */ sfrb(LCDM8,LCDM8_); #define LCDM9_ LCD_BASE+0x9 /* LCD memory 9 */ sfrb(LCDM9,LCDM9_); #define LCDM10_ LCD_BASE+0xA /* LCD memory 10 */ sfrb(LCDM10,LCDM10_); #define LCDM11_ LCD_BASE+0xB /* LCD memory 11 */ sfrb(LCDM11,LCDM11_); #define LCDM12_ LCD_BASE+0xC /* LCD memory 12 */ sfrb(LCDM12,LCDM12_); #define LCDM13_ LCD_BASE+0xD /* LCD memory 13 */ sfrb(LCDM13,LCDM13_); #define LCDM14_ LCD_BASE+0xE /* LCD memory 14 */ sfrb(LCDM14,LCDM14_); #define LCDM15_ LCD_BASE+0xF /* LCD memory 15 */ sfrb(LCDM15,LCDM15_); #define LCDMA_ LCDM10_ /* LCD memory A */ sfrb(LCDMA,LCDMA_); #define LCDMB_ LCDM11_ /* LCD memory B */ sfrb(LCDMB,LCDMB_); #define LCDMC_ LCDM12_ /* LCD memory C */ sfrb(LCDMC,LCDMC_); #define LCDMD_ LCDM13_ /* LCD memory D */ sfrb(LCDMD,LCDMD_); #define LCDME_ LCDM14_ /* LCD memory E */ sfrb(LCDME,LCDME_); #define LCDMF_ LCDM15_ /* LCD memory F */ sfrb(LCDMF,LCDMF_); #if defined(__msp430_have_lcd_16_20) #define LCDM16_ LCD_BASE+0x10 /* LCD memory 16 */ sfrb(LCDM16,LCDM16_); #define LCDM17_ LCD_BASE+0x11 /* LCD memory 17 */ sfrb(LCDM17,LCDM17_); #define LCDM18_ LCD_BASE+0x12 /* LCD memory 18 */ sfrb(LCDM18,LCDM18_); #define LCDM19_ LCD_BASE+0x13 /* LCD memory 19 */ sfrb(LCDM19,LCDM19_); #define LCDM20_ LCD_BASE+0x14 /* LCD memory 20 */ sfrb(LCDM20,LCDM20_); #endif #endif Index: basic_clock.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/basic_clock.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -w -d -r1.4 -r1.5 --- basic_clock.h 4 Mar 2003 15:49:45 -0000 1.4 +++ basic_clock.h 11 Mar 2005 15:49:50 -0000 1.5 @@ -12,7 +12,9 @@ * $Id$ */ -/* Switches: none */ +/* Switches: +__msp430_have_basic_clock_plus +*/ #define DCOCTL_ 0x0056 /* DCO Clock Frequency Control */ sfrb (DCOCTL,DCOCTL_); @@ -20,6 +22,10 @@ sfrb (BCSCTL1,BCSCTL1_); #define BCSCTL2_ 0x0058 /* Basic Clock System Control 2 */ sfrb (BCSCTL2,BCSCTL2_); +#if defined(__msp430_have_basic_clock_plus) +#define BCSCTL3_ 0x0053 /* Basic Clock System Control 3 */ +sfrb(BCSCTL3, BCSCTL3_); +#endif #define MOD0 0x01 /* Modulation Bit 0 */ #define MOD1 0x02 /* Modulation Bit 1 */ @@ -44,7 +50,9 @@ #define DIVA_2 (2<<4) /* ACLK Divider 2: /4 */ #define DIVA_3 (3<<4) /* ACLK Divider 3: /8 */ +#if !defined(__msp430_have_basic_clock_plus) #define DCOR 0x01 /* Enable External Resistor : 1 */ +#endif #define DIVS0 0x02 /* SMCLK Divider 0 */ #define DIVS1 0x04 /* SMCLK Divider 1 */ #define SELS 0x08 /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ @@ -68,6 +76,32 @@ #define SELM_2 (2<<6) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ #define SELM_3 (3<<6) /* MCLK Source Select 3: LFXTCLK */ +#if defined(__msp430_have_basic_clock_plus) +#define LFXT1OF 0x01 /* Low/high Frequency Oscillator Fault Flag */ +#define XT2OF 0x02 /* High frequency oscillator 2 fault flag */ +#define XCAP0 0x04 /* XIN/XOUT Cap 0 */ +#define XCAP1 0x08 /* XIN/XOUT Cap 1 */ +#define LFXT1S0 0x10 /* Mode 0 for LFXT1 (XTS = 0) */ +#define LFXT1S1 0x20 /* Mode 1 for LFXT1 (XTS = 0) */ +#define XT2S0 0x40 /* Mode 0 for XT2 */ +#define XT2S1 0x80 /* Mode 1 for XT2 */ + +#define XCAP_0 (0<<2) /* XIN/XOUT Cap : 0 pF */ +#define XCAP_1 (1<<2) /* XIN/XOUT Cap : 6 pF */ +#define XCAP_2 (2<<2) /* XIN/XOUT Cap : 10 pF */ +#define XCAP_3 (3<<2) /* XIN/XOUT Cap : 12.5 pF */ + +#define LFXT1S_0 (0<<4) /* Mode 0 for LFXT1 : Normal operation */ +#define LFXT1S_1 (1<<4) /* Mode 1 for LFXT1 : Bypass amplitude regulation */ +#define LFXT1S_2 (2<<4) /* Mode 2 for LFXT1 : Reserved */ +#define LFXT1S_3 (3<<4) /* Mode 3 for LFXT1 : Digital input signal */ + +#define XT2S_0 (0<<6) /* Mode 0 for XT2 : 0.4 - 1 MHz */ +#define XT2S_1 (1<<6) /* Mode 1 for XT2 : 1 - 4 MHz */ +#define XT2S_2 (2<<6) /* Mode 2 for XT2 : 2 - 16 MHz */ +#define XT2S_3 (3<<6) /* Mode 3 for XT2 : Digital input signal */ +#endif + /* Aliases by mspgcc */ #define DIVA_DIV1 DIVA_0 #define DIVA_DIV2 DIVA_1 Index: compa.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/compa.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -w -d -r1.3 -r1.4 --- compa.h 28 Dec 2002 06:56:14 -0000 1.3 +++ compa.h 11 Mar 2005 15:49:50 -0000 1.4 @@ -12,7 +12,9 @@ * $Id$ */ -/* Switches: none */ +/* Switches: +__msp430_have_compa_extended mux +*/ #define CACTL1_ 0x0059 /* Comparator A Control 1 */ sfrb(CACTL1,CACTL1_); @@ -39,10 +41,17 @@ #define CAF 0x02 /* Comp. A Enable Output Filter */ #define P2CA0 0x04 /* Comp. A Connect External Signal to CA0 : 1 */ #define P2CA1 0x08 /* Comp. A Connect External Signal to CA1 : 1 */ +#if defined(__msp430_have_compa_extended mux) +#define P2CA2 0x10 /* Comp. A -Terminal Multiplexer */ +#define P2CA3 0x20 /* Comp. A -Terminal Multiplexer */ +#define P2CA4 0x40 /* Comp. A +Terminal Multiplexer */ +#define CASHORT 0x80 /* Comp. A Short + and - Terminals */ +#else #define CACTL24 0x10 #define CACTL25 0x20 #define CACTL26 0x40 #define CACTL27 0x80 +#endif #define CAPD0 0x01 /* Comp. A Disable Input Buffer of Port Register .0 */ #define CAPD1 0x02 /* Comp. A Disable Input Buffer of Port Register .1 */ Index: esp430e.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/esp430e.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -w -d -r1.3 -r1.4 --- esp430e.h 28 Aug 2003 15:06:49 -0000 1.3 +++ esp430e.h 11 Mar 2005 15:49:50 -0000 1.4 @@ -105,10 +105,10 @@ #define REACTENERGY_HI RET13 /* Reactive energy High Word */ #define APPENERGY_LO RET14 /* Apparent energy Low Word */ #define APPENERGY_HI RET15 /* Apparent energy High Word */ -#define ACTENSPER1_LO RET16 /* Active energy I1 for last mains periode Low Word */ -#define ACTENSPER1_HI RET17 /* Active energy I1 for last mains periode High Word */ -#define ACTENSPER2_LO RET18 /* Active energy I2 for last mains periode Low Word */ -#define ACTENSPER2_HI RET19 /* Active energy I2 for last mains periode High Word */ +#define ACTENSPER1_LO RET16 /* Active energy I1 for last mains period Low Word */ +#define ACTENSPER1_HI RET17 /* Active energy I1 for last mains period High Word */ +#define ACTENSPER2_LO RET18 /* Active energy I2 for last mains period Low Word */ +#define ACTENSPER2_HI RET19 /* Active energy I2 for last mains period High Word */ #define POWERFCT RET20 /* Power factor */ #define CAPIND RET21 /* Power factor: neg: inductive pos: cap. (LowByte)*/ #define MAINSPERIOD RET22 /* Mains period */ Index: flash.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/flash.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -w -d -r1.3 -r1.4 --- flash.h 28 Dec 2002 06:53:54 -0000 1.3 +++ flash.h 11 Mar 2005 15:49:50 -0000 1.4 @@ -12,7 +12,9 @@ * $Id$ */ -/* Switches: none */ +/* Switches: +__msp430_have_flash_extra_flags +*/ #define FCTL1_ 0x0128 /* FLASH Control 1 */ sfrw (FCTL1,FCTL1_); @@ -27,6 +29,10 @@ #define ERASE 0x0002 /* Enable bit for flash segment erase */ #define MERAS 0x0004 /* Enable bit for flash mass erase */ +#if defined(__msp430_have_flash_extra_flags) +#define EEI 0x0008 /* Enable Erase Interrupts */ +#define EEIEX 0x0010 /* Enable Emergency Interrupt Exit */ +#endif #define WRT 0x0040 /* Enable bit for flash write */ #define BLKWRT 0x0080 /* Enable bit for flash segment write */ #define SEGWRT 0x0080 /* old definition */ /* Enable bit for Flash segment write */ @@ -51,6 +57,10 @@ #define WAIT 0x0008 /* Wait flag for segment write */ #define LOCK 0x0010 /* Lock bit: 1 - Flash is locked (read only) */ #define EMEX 0x0020 /* Flash Emergency Exit */ +#if defined(__msp430_have_flash_extra_flags) +#define LOCKA 0x0040 /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +#define FAIL 0x0080 /* Last Program or Erase failed */ +#endif /* Aliases by mspgcc */ #define FSSEL_ACLK FSSEL_0 Index: lcd.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/lcd.h,v retrieving revision 1.5 retrieving revision 1.6 diff -u -w -d -r1.5 -r1.6 --- lcd.h 15 Jun 2004 13:50:15 -0000 1.5 +++ lcd.h 11 Mar 2005 15:49:50 -0000 1.6 @@ -1,4 +1,3 @@ - #ifndef __msp430_headers_lcd_h #define __msp430_headers_lcd_h @@ -17,6 +16,7 @@ LCD_BASE - base address of LCD module __msp430_have_lcdlowr - if LCD controller supports the LCDLOWR bit +__msp430_have_lcd_16_20 - if LCD controller supports memory locations 16 to 20 */ @@ -61,7 +61,7 @@ #define LCDOGOFF (LCDP2|LCDP1|LCDP0) /* S0 - S39 */ #define LCDMEM_ LCD_BASE+1 /* LCD memory */ -#ifdef _GNU_ASSEMBLER_ +#if defined(_GNU_ASSEMBLER_) #define LCDMEM LCDMEM_ /* LCD memory (for assembler) */ #else #define LCDMEM ((char*) LCDMEM_) /* LCD memory (for C) */ @@ -110,8 +110,7 @@ #define LCDMF_ LCDM15_ /* LCD memory F */ sfrb(LCDMF,LCDMF_); -#ifdef __msp430_have_lcd_16_20 - +#if defined(__msp430_have_lcd_16_20) #define LCDM16_ LCD_BASE+0x10 /* LCD memory 16 */ sfrb(LCDM16,LCDM16_); #define LCDM17_ LCD_BASE+0x11 /* LCD memory 17 */ @@ -122,7 +121,6 @@ sfrb(LCDM19,LCDM19_); #define LCDM20_ LCD_BASE+0x14 /* LCD memory 20 */ sfrb(LCDM20,LCDM20_); - #endif #endif Index: opamp.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/opamp.h,v retrieving revision 1.4 retrieving revision 1.5 diff -u -w -d -r1.4 -r1.5 --- opamp.h 4 Nov 2004 00:18:58 -0000 1.4 +++ opamp.h 11 Mar 2005 15:49:50 -0000 1.5 @@ -12,66 +12,108 @@ * $Id$ */ -/* Switches: none */ +/* Switches: +__msp430_have_opamp_1 +__msp430_have_opamp_2 +__msp430_have_opamp_feedback_taps +__msp430_have_opamp_switches +__msp430_have_opamp_output_select +__msp430_have_opamp_rail_to_rail +__msp430_have_opamp_offset_cal +*/ + #define OA0CTL0_ 0x00C0 /* OA0 Control register 0 */ sfrb(OA0CTL0, OA0CTL0_); -#define OA0CTL1_ 0x00C1 /* OA0 Control register 1 */ -sfrb(OA0CTL1, OA0CTL1_); -#define OA1CTL0_ 0x00C2 /* OA1 Control register 0 */ -sfrb(OA1CTL0, OA1CTL0_); #define OA1CTL1_ 0x00C3 /* OA1 Control register 1 */ sfrb(OA1CTL1, OA1CTL1_); + +#if defined(__msp430_have_opamp_1) +#define OA0CTL1_ 0x00C1 /* OA0 Control register 1 */ +sfrb(OA0CTL1, OA0CTL1_); #define OA2CTL0_ 0x00C4 /* OA2 Control register 0 */ sfrb(OA2CTL0, OA2CTL0_); +#endif + +#if defined(__msp430_have_opamp_2) +#define OA1CTL0_ 0x00C2 /* OA1 Control register 0 */ +sfrb(OA1CTL0, OA1CTL0_); #define OA2CTL1_ 0x00C5 /* OA2 Control register 1 */ sfrb(OA2CTL1, OA2CTL1_); +#endif -#define OAADC0 (0x01) /* OAx output to ADC12 input channel select 0 */ -#define OAADC1 (0x02) /* OAx output to ADC12 input channel select 1 */ -#define OAPM0 (0x04) /* OAx Power mode select 0 */ -#define OAPM1 (0x08) /* OAx Power mode select 1 */ -#define OAP0 (0x10) /* OAx Inverting input select 0 */ -#define OAP1 (0x20) /* OAx Inverting input select 1 */ -#define OAN0 (0x40) /* OAx Non-inverting input select 0 */ -#define OAN1 (0x80) /* OAx Non-inverting input select 1 */ +#if defined(__msp430_have_opamp_switches) +#define SWCTL_ 0x00CF /* OA Analog Switches Control Register */ +sfrb(SWCTL, SWCTL_) +#endif -#define OAPM_0 (0x00) /* OAx Power mode select: off */ -#define OAPM_1 (0x04) /* OAx Power mode select: slow */ -#define OAPM_2 (0x08) /* OAx Power mode select: medium */ -#define OAPM_3 (0x0C) /* OAx Power mode select: fast */ -#define OAP_0 (0x00) /* OAx Inverting input select 00 */ -#define OAP_1 (0x10) /* OAx Inverting input select 01 */ -#define OAP_2 (0x20) /* OAx Inverting input select 10 */ -#define OAP_3 (0x30) /* OAx Inverting input select 11 */ -#define OAN_0 (0x40) /* OAx Non-inverting input select 00 */ -#define OAN_1 (0x40) /* OAx Non-inverting input select 01 */ -#define OAN_2 (0x80) /* OAx Non-inverting input select 10 */ -#define OAN_3 (0x40) /* OAx Non-inverting input select 11 */ +#if defined(__msp430_have_opamp_output_select) +#define OAADC0 0x01 /* OAx output to ADC12 input channel select 0 */ +#define OAADC1 0x02 /* OAx output to ADC12 input channel select 1 */ +#endif +#define OAPM0 0x04 /* OAx Power mode select 0 */ +#define OAPM1 0x08 /* OAx Power mode select 1 */ +#define OAP0 0x10 /* OAx Inverting input select 0 */ +#define OAP1 0x20 /* OAx Inverting input select 1 */ +#define OAN0 0x40 /* OAx Non-inverting input select 0 */ +#define OAN1 0x80 /* OAx Non-inverting input select 1 */ -#define OARRIP (0x01) /* OAx Rail-to-Rail Input off */ -//#define Reserved (0x02) /* */ -#define OAFC0 (0x04) /* OAx Function control 0 */ -#define OAFC1 (0x08) /* OAx Function control 1 */ -#define OAFC2 (0x10) /* OAx Function control 2 */ -#define OAFBR0 (0x20) /* OAx Feedback resistor select 0 */ -#define OAFBR1 (0x40) /* OAx Feedback resistor select 1 */ -#define OAFBR2 (0x80) /* OAx Feedback resistor select 2 */ +#define OAPM_0 (0<<2) /* OAx Power mode select: off */ +#define OAPM_1 (1<<2) /* OAx Power mode select: slow */ +#define OAPM_2 (2<<2) /* OAx Power mode select: medium */ +#define OAPM_3 (3<<2) /* OAx Power mode select: fast */ +#define OAP_0 (0<<4) /* OAx Inverting input select 00 */ +#define OAP_1 (1<<4) /* OAx Inverting input select 01 */ +#define OAP_2 (2<<4) /* OAx Inverting input select 10 */ +#define OAP_3 (3<<4) /* OAx Inverting input select 11 */ +#define OAN_0 (0<<6) /* OAx Non-inverting input select 00 */ +#define OAN_1 (1<<6) /* OAx Non-inverting input select 01 */ +#define OAN_2 (2<<6) /* OAx Non-inverting input select 10 */ +#define OAN_3 (3<<6) /* OAx Non-inverting input select 11 */ -#define OAFC_0 (0x00) /* OAx Function: Gen. Purpose */ -#define OAFC_1 (0x04) /* OAx Function: Comparing */ -#define OAFC_2 (0x08) /* OAx Function: Reserved */ -#define OAFC_3 (0x0C) /* OAx Function: Differential */ -#define OAFC_4 (0x10) /* OAx Function: Non-Inverting, PGA */ -#define OAFC_5 (0x14) /* OAx Function: Reserved */ -#define OAFC_6 (0x18) /* OAx Function: Inverting */ -#define OAFC_7 (0x1C) /* OAx Function: Differential */ -#define OAFBR_0 (0x00) /* OAx Feedback resistor: Tap 0 */ -#define OAFBR_1 (0x20) /* OAx Feedback resistor: Tap 1 */ -#define OAFBR_2 (0x40) /* OAx Feedback resistor: Tap 2 */ -#define OAFBR_3 (0x60) /* OAx Feedback resistor: Tap 3 */ -#define OAFBR_4 (0x80) /* OAx Feedback resistor: Tap 4 */ -#define OAFBR_5 (0xA0) /* OAx Feedback resistor: Tap 5 */ -#define OAFBR_6 (0xC0) /* OAx Feedback resistor: Tap 6 */ -#define OAFBR_7 (0xE0) /* OAx Feedback resistor: Tap 7 */ +#if defined(__msp430_have_opamp_rail_to_rail) +#define OARRIP 0x01 /* OAx Rail-to-Rail Input off */ +#endif +#if defined(__msp430_have_opamp_offset_cal) +#define OACAL 0x02 /* OAx Offset Calibration */ +#endif +#define OAFC0 0x04 /* OAx Function control 0 */ +#define OAFC1 0x08 /* OAx Function control 1 */ +#define OAFC2 0x10 /* OAx Function control 2 */ +#if defined(__msp430_have_opamp_feedback_taps) +#define OAFBR0 0x20 /* OAx Feedback resistor select 0 */ +#define OAFBR1 0x40 /* OAx Feedback resistor select 1 */ +#define OAFBR2 0x80 /* OAx Feedback resistor select 2 */ +#endif + +#define OAFC_0 (0<<2) /* OAx Function: Gen. Purpose */ +#define OAFC_1 (1<<2) /* OAx Function: Comparing */ +#define OAFC_2 (2<<2) /* OAx Function: Reserved */ +#define OAFC_3 (3<<2) /* OAx Function: Differential */ +#define OAFC_4 (4<<2) /* OAx Function: Non-Inverting, PGA */ +#define OAFC_5 (5<<2) /* OAx Function: Reserved */ +#define OAFC_6 (6<<2) /* OAx Function: Inverting */ +#define OAFC_7 (7<<2) /* OAx Function: Differential */ + +#if defined(__msp430_have_opamp_feedback_taps) +#define OAFBR_0 (0<<5) /* OAx Feedback resistor: Tap 0 */ +#define OAFBR_1 (1<<5) /* OAx Feedback resistor: Tap 1 */ +#define OAFBR_2 (2<<5) /* OAx Feedback resistor: Tap 2 */ +#define OAFBR_3 (3<<5) /* OAx Feedback resistor: Tap 3 */ +#define OAFBR_4 (4<<5) /* OAx Feedback resistor: Tap 4 */ +#define OAFBR_5 (5<<5) /* OAx Feedback resistor: Tap 5 */ +#define OAFBR_6 (6<<5) /* OAx Feedback resistor: Tap 6 */ +#define OAFBR_7 (7<<5) /* OAx Feedback resistor: Tap 7 */ +#endif + +#if defined(__msp430_have_opamp_switches) +#define SWCTL0 0x01 /* OA Analog Switch Control 0 */ +#define SWCTL1 0x02 /* OA Analog Switch Control 1 */ +#define SWCTL2 0x04 /* OA Analog Switch Control 2 */ +#define SWCTL3 0x08 /* OA Analog Switch Control 3 */ +#define SWCTL4 0x10 /* OA Analog Switch Control 4 */ +#define SWCTL5 0x20 /* OA Analog Switch Control 5 */ +#define SWCTL6 0x40 /* OA Analog Switch Control 6 */ +#define SWCTL7 0x80 /* OA Analog Switch Control 7 */ +#endif #endif Index: sd16.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/sd16.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -w -d -r1.3 -r1.4 --- sd16.h 15 Jun 2004 13:50:15 -0000 1.3 +++ sd16.h 11 Mar 2005 15:49:50 -0000 1.4 @@ -12,37 +12,71 @@ * $Id$ */ -/* Switches: none */ +/* Switches: + +__msp430_have_sd16a - the SD16 is the "A" type +__msp430_have_sd16_1 +__msp430_have_sd16_2 +*/ + +#define SD16CTL_ 0x0100 /* Sigma Delta ADC 16 Control Register */ +sfrw(SD16CTL, SD16CTL_); +#define SD16IV_ 0x0110 /* SD16 Interrupt Vector Register */ +sfrw(SD16IV, SD16IV_); + +#if defined(__msp430_have_sd16a) +#define SD16AE_ 0x00B7 /* SD16 Analog Input Enable Register */ +srfb(SD16AE, SD16AE_); +#else +#define SD16CONF0_ 0x00B7 /* SD16 Internal Configuration Register 0 */ +sfrb(SD16CONF0, SD16CONF0_); +#define SD16CONF1_ 0x00BF /* SD16 Internal Configuration Register 1 */ +sfrb(SD16CONF0, SD16CONF0_); + /* Please use only the recommended settings */ +#endif #define SD16INCTL0_ 0x00B0 /* SD16 Input Control Register Channel 0 */ sfrb(SD16INCTL0, SD16INCTL0_); -#define SD16INCTL1_ 0x00B1 /* SD16 Input Control Register Channel 1 */ -sfrb(SD16INCTL1, SD16INCTL1_); -#define SD16INCTL2_ 0x00B2 /* SD16 Input Control Register Channel 2 */ -sfrb(SD16INCTL2, SD16INCTL2_); #define SD16PRE0_ 0x00B8 /* SD16 Preload Register Channel 0 */ sfrb(SD16PRE0, SD16PRE0_); -#define SD16PRE1_ 0x00B9 /* SD16 Preload Register Channel 1 */ -sfrb(SD16PRE1, SD16PRE1_); -#define SD16PRE2_ 0x00BA /* SD16 Preload Register Channel 2 */ -sfrb(SD16PRE2, SD16PRE2_); - -#define SD16CTL_ 0x0100 /* Sigma Delta ADC 16 Control Register */ -sfrw(SD16CTL, SD16CTL_); #define SD16CCTL0_ 0x0102 /* SD16 Channel 0 Control Register */ sfrw(SD16CCTL0, SD16CCTL0_); -#define SD16CCTL1_ 0x0104 /* SD16 Channel 1 Control Register */ -sfrw(SD16CCTL1, SD16CCTL1_); -#define SD16CCTL2_ 0x0106 /* SD16 Channel 2 Control Register */ -sfrw(SD16CCTL2, SD16CCTL2_); -#define SD16IV_ 0x0110 /* SD16 Interrupt Vector Register */ -sfrw(SD16IV, SD16IV_); #define SD16MEM0_ 0x0112 /* SD16 Channel 0 Conversion Memory */ sfrw(SD16MEM0, SD16MEM0_); + +#if defined(__msp430_have_sd16_1) +#define SD16INCTL1_ 0x00B1 /* SD16 Input Control Register Channel 1 */ +sfrb(SD16INCTL1, SD16INCTL1_); +#define SD16PRE1_ 0x00B9 /* SD16 Preload Register Channel 1 */ +sfrb(SD16PRE1, SD16PRE1_); +#define SD16CCTL1_ 0x0104 /* SD16 Channel 1 Control Register */ +sfrw(SD16CCTL1, SD16CCTL1_); #define SD16MEM1_ 0x0114 /* SD16 Channel 1 Conversion Memory */ sfrw(SD16MEM1, SD16MEM1_); +#endif + +#if defined(__msp430_have_sd16_2) +#define SD16INCTL2_ 0x00B2 /* SD16 Input Control Register Channel 2 */ +sfrb(SD16INCTL2, SD16INCTL2_); +#define SD16PRE2_ 0x00BA /* SD16 Preload Register Channel 2 */ +sfrb(SD16PRE2, SD16PRE2_); +#define SD16CCTL2_ 0x0106 /* SD16 Channel 2 Control Register */ +sfrw(SD16CCTL2, SD16CCTL2_); #define SD16MEM2_ 0x0116 /* SD16 Channel 2 Conversion Memory */ sfrw(SD16MEM2, SD16MEM2_); +#endif + +#if defined(__msp430_have_sd16a) +/* SD16AE */ +#define SD16AE0 0x0001 /* SD16 External Input Enable 0 */ +#define SD16AE1 0x0002 /* SD16 External Input Enable 1 */ +#define SD16AE2 0x0004 /* SD16 External Input Enable 2 */ +#define SD16AE3 0x0008 /* SD16 External Input Enable 3 */ +#define SD16AE4 0x0010 /* SD16 External Input Enable 4 */ +#define SD16AE5 0x0020 /* SD16 External Input Enable 5 */ +#define SD16AE6 0x0040 /* SD16 External Input Enable 6 */ +#define SD16AE7 0x0080 /* SD16 External Input Enable 7 */ +#endif /* SD16INCTLx - AFEINCTLx */ #define SD16INCH0 0x0001 /* SD16 Input Channel select 0 */ @@ -70,20 +104,37 @@ #define SD16INCH_6 (6<<0) /* SD16 Input Channel select Temp */ #define SD16INCH_7 (7<<0) /* SD16 Input Channel select Offset */ +#define SD16INTDLY_0 (0<<6) /* SD16 Interrupt Delay: Int. after 4.Conversion */ +#define SD16INTDLY_1 (1<<6) /* SD16 Interrupt Delay: Int. after 3.Conversion */ +#define SD16INTDLY_2 (2<<6) /* SD16 Interrupt Delay: Int. after 2.Conversion */ +#define SD16INTDLY_3 (3<<6) /* SD16 Interrupt Delay: Int. after 1.Conversion */ + /* SD16CTL - AFECTL */ #define SD16OVIE 0x0002 /* Overflow Interupt Enable */ #define SD16REFON 0x0004 /* Switch internal Reference on */ #define SD16VMIDON 0x0008 /* Switch Vmid Buffer on */ -#define SD16SSEL0 0x0010 /* AFE Clock Source Select 0 */ -#define SD16SSEL1 0x0020 /* AFE Clock Source Select 1 */ -#define SD16DIV0 0x0040 /* AFE Clock Divider Select 0 */ -#define SD16DIV1 0x0080 /* AFE Clock Divider Select 1 */ -#define SD16LP 0x0100 /* AFE Low Power Mode Enable */ +#define SD16SSEL0 0x0010 /* SD16 Clock Source Select 0 */ +#define SD16SSEL1 0x0020 /* SD16 Clock Source Select 1 */ +#define SD16DIV0 0x0040 /* SD16 Clock Divider Select 0 */ +#define SD16DIV1 0x0080 /* SD16 Clock Divider Select 1 */ +#define SD16LP 0x0100 /* SD16 Low Power Mode Enable */ +#if defined(__msp430_have_sd16a) +#define SD16XDIV0 0x0200 /* SD16 2.Clock Divider Select 0 */ +#define SD16XDIV1 0x0400 /* SD16 2.Clock Divider Select 1 */ +//#define SD16XDIV2 0x0800) /* SD16 2.Clock Divider Select 2 */ +#endif -#define SD16DIV_0 (0x0000) /* AFE Clock Divider Select /1 */ -#define SD16DIV_1 (SD16DIV0) /* AFE Clock Divider Select /2 */ -#define SD16DIV_2 (SD16DIV1) /* AFE Clock Divider Select /4 */ -#define SD16DIV_3 (SD16DIV0|SD16DIV1) /* AFE Clock Divider Select /8 */ +#define SD16DIV_0 (0x0000) /* SD16 Clock Divider Select /1 */ +#define SD16DIV_1 (SD16DIV0) /* SD16 Clock Divider Select /2 */ +#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */ +#define SD16DIV_3 (SD16DIV0|SD16DIV1) /* SD16 Clock Divider Select /8 */ + +#if defined(__msp430_have_sd16a) +#define SD16XDIV_0 (0x0000) /* SD16 2.Clock Divider Select /1 */ +#define SD16XDIV_1 (SD16XDIV0) /* SD16 2.Clock Divider Select /3 */ +#define SD16XDIV_2 (SD16XDIV1) /* SD16 2.Clock Divider Select /16 */ +#define SD16XDIV_3 (SD16XDIV0|SD16XDIV1) /* SD16 2.Clock Divider Select /48 */ +#endif #define SD16SSEL_0 (0x0000) /* AFE Clock Source Select MCLK */ #define SD16SSEL_1 (SD16SSEL0) /* AFE Clock Source Select SMCLK */ @@ -99,21 +150,41 @@ #define SD16OVIFG 0x0020 /* SD16 Channel x Overflow Interrupt Flag */ #define SD16LSBACC 0x0040 /* SD16 Channel x Access LSB of ADC */ #define SD16LSBTOG 0x0080 /* SD16 Channel x Toggle LSB Output of ADC */ -#define SD16OSR0 0x0100 /* AFE Channel x OverSampling Ratio 0 */ -#define SD16OSR1 0x0200 /* AFE Channel x OverSampling Ratio 1 */ +#define SD16OSR0 0x0100 /* SD16 Channel x OverSampling Ratio 0 */ +#define SD16OSR1 0x0200 /* SD16 Channel x OverSampling Ratio 1 */ #define SD16SNGL 0x0400 /* SD16 Channel x Single Conversion On/Off */ +#if defined(__msp430_have_sd16a) +#define SD16XOSR 0x0800 /* SD16 Channel x Extended OverSampling Ratio */ +#define SD16UNI 0x1000 /* SD16 Channel x Bipolar(0) / Unipolar(1) Mode */ +#define SD16BUF0 0x2000 /* SD16 Channel x High Impedance Input Buffer Select: 0 */ +#define SD16BUF1 0x4000 /* SD16 Channel x High Impedance Input Buffer Select: 1 */ +#define SD16BUFG 0x8000 /* SD16 Channel x Buffer Gain 0:Gain=1 / 1:Gain=2 */ +#endif -#define SD16OSR_256 (0<<8) /* AFE Channel x OverSampling Ratio 256 */ -#define SD16OSR_128 (1<<8) /* AFE Channel x OverSampling Ratio 128 */ -#define SD16OSR_64 (2<<8) /* AFE Channel x OverSampling Ratio 64 */ -#define SD16OSR_32 (3<<8) /* AFE Channel x OverSampling Ratio 32 */ +#if defined(__msp430_have_sd16a) +#define SD16OSR_1024 (SD16XOSR|SD16OSR0) /* SD16 Channel x OverSampling Ratio 1024 */ +#define SD16OSR_512 (SD16XOSR) /* SD16 Channel x OverSampling Ratio 512 */ +#endif +#define SD16OSR_256 (0<<8) /* SD16 Channel x OverSampling Ratio 256 */ +#define SD16OSR_128 (1<<8) /* SD16 Channel x OverSampling Ratio 128 */ +#define SD16OSR_64 (2<<8) /* SD16 Channel x OverSampling Ratio 64 */ +#define SD16OSR_32 (3<<8) /* SD16 Channel x OverSampling Ratio 32 */ -#define AFEINCTL0 SD16INCTL0 /* AFE Input Control Register Channel 0 */ -#define AFEINCTL1 SD16INCTL1 /* AFE Input Control Register Channel 1 */ -#define AFEINCTL2 SD16INCTL2 /* AFE Input Control Register Channel 2 */ -#define AFECTL SD16CTL /* AFE Control Register */ -#define AFECCTL0 SD16CCTL0 /* AFE Channel 0 Control Register */ -#define AFECCTL1 SD16CCTL1 /* AFE Channel 1 Control Register */ -#define AFECCTL2 SD16CCTL02 /* AFE Channel 2 Control Register */ +#if defined(__msp430_have_sd16a) +#define SD16BUF_0 (0<<13) /* SD16 High Imp. Input Buffer: Disabled */ +#define SD16BUF_1 (1<<13) /* SD16 High Imp. Input Buffer: Slow */ +#define SD16BUF_2 (2<<13) /* SD16 High Imp. Input Buffer: Meduim */ +#define SD16BUF_3 (3<<13) /* SD16 High Imp. Input Buffer: Fast */ +#endif + +#if !defined(__msp430_have_sd16a) +#define AFEINCTL0 SD16INCTL0 /* SD16 Input Control Register Channel 0 */ +#define AFEINCTL1 SD16INCTL1 /* SD16 Input Control Register Channel 1 */ +#define AFEINCTL2 SD16INCTL2 /* SD16 Input Control Register Channel 2 */ +#define AFECTL SD16CTL /* SD16 Control Register */ +#define AFECCTL0 SD16CCTL0 /* SD16 Channel 0 Control Register */ +#define AFECCTL1 SD16CCTL1 /* SD16 Channel 1 Control Register */ +#define AFECCTL2 SD16CCTL02 /* SD16 Channel 2 Control Register */ +#endif #endif ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. 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