CVS: msp430-libc/include/msp430 timera.h,1.10,1.11

Update of /cvsroot/mspgcc/msp430-libc/include/msp430
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv8345/msp430-libc/include/msp430

Modified Files:
	timera.h 
Log Message:
Now allows for timerA2 for the new 20xx devices


Index: timera.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timera.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -w -d -r1.10 -r1.11
--- timera.h	17 Aug 2005 14:28:46 -0000	1.10
+++ timera.h	5 Sep 2005 13:04:47 -0000	1.11
@@ -14,62 +14,75 @@
 
 /* Switches: 
 
+__MSP430_HAS_TA2__  - if the device has a timer0 A with 2 channels
+__MSP430_HAS_TA3__  - if the device has a timer0 A with 3 channels
 __MSP430_HAS_T1A5__ - if the device has a timer1 A, as well as timer0 A
 
 */
 
+#if defined(__MSP430_HAS_TA2__)  || defined(__MSP430_HAS_TA3__)
 #define TA0IV_              0x012E  /* Timer A 0 Interrupt Vector Word */
 sfrw (TA0IV,TA0IV_);
 #define TA0CTL_             0x0160  /* Timer A 0 Control */
 sfrw (TA0CTL,TA0CTL_);
+#define TA0R_               0x0170  /* Timer A 0 */
+sfrw (TA0R,TA0R_);
+
 #define TA0CCTL0_           0x0162  /* Timer A 0 Capture/Compare Control 0 */
 sfrw (TA0CCTL0,TA0CCTL0_);
 #define TA0CCTL1_           0x0164  /* Timer A 0 Capture/Compare Control 1 */
 sfrw (TA0CCTL1,TA0CCTL1_);
-#define TA0CCTL2_           0x0166  /* Timer A 0 Capture/Compare Control 2 */
-sfrw (TA0CCTL2,TA0CCTL2_);
-#define TA0R_               0x0170  /* Timer A 0 */
-sfrw (TA0R,TA0R_);
 #define TA0CCR0_            0x0172  /* Timer A 0 Capture/Compare 0 */
 sfrw (TA0CCR0,TA0CCR0_);
 #define TA0CCR1_            0x0174  /* Timer A 0 Capture/Compare 1 */
 sfrw (TA0CCR1,TA0CCR1_);
-#define TA0CCR2_            0x0176  /* Timer A 0 Capture/Compare 2 */
-sfrw (TA0CCR2,TA0CCR2_);
 
 /* Alternate register names */
 #define TAIV                TA0IV
-#define TACTL               TA0CTL
-#define TACCTL0             TA0CCTL0
-#define TACCTL1             TA0CCTL1
-#define TACCTL2             TA0CCTL2
-#define TAR                 TA0R
-#define TACCR0              TA0CCR0
-#define TACCR1              TA0CCR1
-#define TACCR2              TA0CCR2
 #define TAIV_               TA0IV_
+#define TACTL               TA0CTL
 #define TACTL_              TA0CTL_
+#define TAR                 TA0R
+#define TAR_                TA0R_
+
+#define TACCTL0             TA0CCTL0
 #define TACCTL0_            TA0CCTL0_
+#define TACCTL1             TA0CCTL1
 #define TACCTL1_            TA0CCTL1_
-#define TACCTL2_            TA0CCTL2_
-#define TAR_                TA0R_
+#define TACCR0              TA0CCR0
 #define TACCR0_             TA0CCR0_
+#define TACCR1              TA0CCR1
 #define TACCR1_             TA0CCR1_
-#define TACCR2_             TA0CCR2_
 
 /* Further alternate register names */
 #define CCTL0               TA0CCTL0
-#define CCTL1               TA0CCTL1
-#define CCTL2               TA0CCTL2
-#define CCR0                TA0CCR0
-#define CCR1                TA0CCR1
-#define CCR2                TA0CCR2
 #define CCTL0_              TA0CCTL0_
+#define CCTL1               TA0CCTL1
 #define CCTL1_              TA0CCTL1_
-#define CCTL2_              TA0CCTL2_
+#define CCR0                TA0CCR0
 #define CCR0_               TA0CCR0_
+#define CCR1                TA0CCR1
 #define CCR1_               TA0CCR1_
+#endif
+
+#if defined(__MSP430_HAS_TA3__)
+#define TA0CCTL2_           0x0166  /* Timer A 0 Capture/Compare Control 2 */
+sfrw (TA0CCTL2,TA0CCTL2_);
+#define TA0CCR2_            0x0176  /* Timer A 0 Capture/Compare 2 */
+sfrw (TA0CCR2,TA0CCR2_);
+
+/* Alternate register names */
+#define TACCTL2             TA0CCTL2
+#define TACCTL2_            TA0CCTL2_
+#define TACCR2              TA0CCR2
+#define TACCR2_             TA0CCR2_
+
+/* Further alternate register names */
+#define CCTL2               TA0CCTL2
+#define CCTL2_              TA0CCTL2_
+#define CCR2                TA0CCR2
 #define CCR2_               TA0CCR2_
+#endif
 
 #if defined(__MSP430_HAS_T1A5__)
 #define TA1IV_              0x011E  /* Timer A 1 Interrupt Vector Word */



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