Re: Problem compiling ti example code...
Einar Vading <[email protected]>
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.user |
|---|---|
| Message-ID | <CAB6-VtKgz_fch9Q--P3ERa+puJR8+=bPfagDYYT2srNORM3TYQ@mail.gmail.com> |
The problem is that I use Homebrew for a lot of other stuff and I understand that Homebrew and MacPorts don't work so well together... On Wed, Apr 3, 2013 at 11:30 PM, Aljaž Srebrnič <[email protected]>wrote: > Hey! > If you want, you can try msp430-gcc from MacPorts, you can get it binary, > too. I use it almost daily and it works fine (with eZ430-Chronos). > > Aljaž Srebrnič > > Sent from mobile > -- -- > My public key: http://bit.ly/81qoyC > > On 03/apr/2013, at 23:00, Einar Vading <[email protected]> wrote: > > > I am trying to use mspgcc on my Mac, 10.8.3. > > > > I have managed to build mspgcc but now I can't use it to build the > examples > > from ti (for the launchpad). > > > > This is the code: > > > > > //****************************************************************************** > > // MSP430G2xx1 Demo - Timer_A, Toggle P1.0-2, Cont. Mode ISR, DCO SMCLK > > // > > // Description: Use Timer_A CCRx units and overflow to generate four > > // independent timing intervals. For demonstration, CCR0 and CCR1 output > > // units are optionally selected with port pins P1.1 and P1.2 in toggle > > // mode. As such, these pins will toggle when respective CCRx registers > > match > > // the TAR counter. Interrupts are also enabled with all CCRx units, > > // software loads offset to next interval only - as long as the interval > > offset > > // is aded to CCRx, toggle rate is generated in hardware. Timer_A > overflow > > ISR > > // is used to toggle P1.0 with software. Proper use of the TAIV > interrupt > > // vector generator is demonstrated. > > // ACLK = n/a, MCLK = SMCLK = TACLK = default DCO ~1MHz > > // As coded and assuming ~1MHz DCO, toggle rates are: > > // P1.1 = CCR0 ~ 1MHz/(2*200) ~2500Hz > > // P1.2 = CCR1 ~ 1MHz/(2*1000) ~500Hz > > // P1.0 = overflow ~ 1MHz/(2*65536) ~8Hz > > // > > // MSP430G2xx1 > > // ----------------- > > // /|\| XIN|- > > // | | | > > // --|RST XOUT|- > > // | | > > // | P1.1/TA0|--> CCR0 > > // | P1.2/TA1|--> CCR1 > > // | P1.0|--> Overflow/software > > // > > // D. Dang > > // Texas Instruments Inc. > > // October 2010 > > // Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10 > > > //****************************************************************************** > > > > #include <msp430.h> > > > > int main(void) > > { > > WDTCTL = WDTPW + WDTHOLD; // Stop WDT > > P1SEL |= 0x06; // P1.1 - P1.2 option select > > P1DIR |= 0x07; // P1.0 - P1.2 outputs > > CCTL0 = OUTMOD_4 + CCIE; // CCR0 toggle, interrupt > > enabled > > CCTL1 = OUTMOD_4 + CCIE; // CCR1 toggle, interrupt > > enabled > > TACTL = TASSEL_2 + MC_2 + TAIE; // SMCLK, Contmode, int > enabled > > > > _BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt > > } > > > > // Timer A0 interrupt service routine > > #pragma vector=TIMERA0_VECTOR > > __interrupt void Timer_A0 (void) > > { > > CCR0 += 200; // Add Offset to CCR0 > > } > > > > // Timer_A2 Interrupt Vector (TAIV) handler > > #pragma vector=TIMERA1_VECTOR > > __interrupt void Timer_A1(void) > > { > > switch( TAIV ) > > { > > case 2: CCR1 += 1000; // Add Offset to CCR1 > > break; > > case 10: P1OUT ^= 0x01; // Timer_A3 overflow > > break; > > } > > } > > > > > > And to build it I use: > > > > $ msp430-gcc -mmcu=msp430g2231 -o test.hex test.c -I > > /usr/local/msp430/include/ -L /usr/local/msp430/lib/ -T > > /usr/local/msp430/lib/ldscripts/msp430g2231/memory.x -T > > /usr/local/msp430/lib/ldscripts/msp430g2231/periph.x > > > > Resulting in: > > > > /usr/local/bin/msp430-ld: test.hex section `.init9' will not fit in > region > > `ram' > > /usr/local/bin/msp430-ld: region `ram' overflowed by 10 bytes > > collect2: ld returned 1 exit status > > > > Surely this code can't be to large to fit the device, so what am I > missing? > > > > > > Thanks in advance. > > Einar > > > ------------------------------------------------------------------------------ > > Minimize network downtime and maximize team effectiveness. > > Reduce network management and security costs.Learn how to hire > > the most talented Cisco Certified professionals. Visit the > > Employer Resources Portal > > http://www.cisco.com/web/learning/employer_resources/index.html > > _______________________________________________ > > Mspgcc-users mailing list > > [email protected] > > https://lists.sourceforge.net/lists/listinfo/mspgcc-users > ------------------------------------------------------------------------------ Minimize network downtime and maximize team effectiveness. Reduce network management and security costs.Learn how to hire the most talented Cisco Certified professionals. Visit the Employer Resources Portal http://www.cisco.com/web/learning/employer_resources/index.html _______________________________________________ Mspgcc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mspgcc-users