sequences of length 1 in inline-threaded

Hi,

I see that the inline-threaded interpreter generates sequences of
length 1.

For instructions with the flag BRANCH_OR_CALL set, the address of the
implementation (like for the direct-threaded interpreter) is used in the
code array.  However, for the others, the sequences of length 1 are used.

Example (that I will add to my thesis :) ):
  public static int foo(int a, int b, int c, int d, int e) {
    if (a < 0) {
      return e + 100;
    } else {
      return d;
    }
  }

Gives this switch code:
switch code
 0: ILOAD_0
 1: IFGE
 2: label_1
 ...


And this inline-threaded code:
 0: &&seq_1
 1: &&IFGE
 2: label_2

where seq_1 is a sequence of length 1 with the ILOAD_0 implementation.

Is there a reason of using these 1-instruction sequences?


Thanks,
David

---

David Bélanger
Web page:   http://www.cs.mcgill.ca/~dbelan2/
Public key: http://www.cs.mcgill.ca/~dbelan2/public_key.txt