[qt/clang/llvm]: Summary of bulk changes made

Git repository change summary for qt/clang/llvm
Pushed by mirror-service into branch 'upstream/users/mariusz-sikora-at-amd/gfx13/add-builtins-intrinsics-v-cvt-scalef32-pk32-fp6-f32'.
Changed from 0000000000000000000000000000000000000000 to fc6fa9a27419fb065b960f842f6d1f0c7a69e823
Acknowledgement was received that this change introduces only existing code that has been pushed to another public open source repository.

This change contains the following new commits:

Git commit 334708eb100204edc677a546bfa77ef10df71ec9 by GitHub (on behalf of Nico Weber) on 20/07/2026 at 11:23..
[gn build] Port 03b5c5285eaf (#210688)
https://invent.kde.org/qt/clang/llvm/-/commit/334708eb100204edc677a546bfa77ef10df71ec9

Git commit 41d76f2763a53517f273c87a1a703f00cb965f09 by GitHub (on behalf of Petar Avramovic) on 20/07/2026 at 11:26..
AMDGPU/GlobalISel: Fix G_UNMERGE_VALUES lowering for extended LLTs (#209201)

Use integer type for bit twiddling instead of scalar.
https://invent.kde.org/qt/clang/llvm/-/commit/41d76f2763a53517f273c87a1a703f00cb965f09

Git commit b21fb937f165898c727030760f0a8ab685ef08eb by GitHub (on behalf of Benedek Kaibas) on 20/07/2026 at 11:26..
[analyzer][NFC] Correct the DanglingPtrDeref checker's filename (#209862)

The alpha `DanglingPtrDeref` checker got implemented in #209278. Since
it is under heavy development and subject to change significantly in the
near future it is in alpha stage. During the development of the
`DanglingPtrDeref` checker its name got changed from
`ReportDanglingPtrDeref` to `DanglingPtrDeref` based on the conversation
here:
https://github.com/llvm/llvm-project/pull/209278#discussion_r3578604913

While the checker's registration got updated in `Checkers.td` the same
change did not get applied to the `
clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt` and the checker's
filename. This PR addresses this issue.
https://invent.kde.org/qt/clang/llvm/-/commit/b21fb937f165898c727030760f0a8ab685ef08eb

Git commit 2ec66d76fde71265be83c216d0be3d16bb131fc7 by GitHub (on behalf of Lang Hames) on 20/07/2026 at 11:27..
[orc-rt] Fix wrapper-call managed-code token lifetime (#210686)

d199b284c7d established that ManagedCodeTaskGroup tokens must bracket a
single span of execution on a stack, not a chain of asynchronous
operations (see orc-rt/docs/Design.md's "Managed code execution and
shutdown" section). Session::handleWrapperCall and sendWrapperResult
predated that policy and didn't conform to it: the token was acquired in
handleWrapperCall but only released in sendWrapperResult, holding it for
the whole call/response chain. If Fn deferred sending its result
asynchronously, Session shutdown would incorrectly wait on that deferred
completion instead of proceeding as soon as Fn's stack unwound.

Acquire the token as a TaskGroup::Token scoped to the dispatched call,
and let it release when Fn returns rather than when its result is sent.
https://invent.kde.org/qt/clang/llvm/-/commit/2ec66d76fde71265be83c216d0be3d16bb131fc7

Git commit d90634dc185da79a8eb6a993c28614f4788e368e by GitHub (on behalf of 311Volt) on 20/07/2026 at 11:28..
[offload] support arbitrary memoryFill pattern sizes in L0 plugin (#209724)

Even though L0, CUDA and HSA do not directly support filling memory
regions with non-power-of-two-sized patterns, plugins explicitly allow
for such fills by falling back to a slow path whenever a direct API call
is not possible.

The Level Zero plugin is the odd one out, forwarding directly to
`zeCommandListAppendMemoryFill`. This fails for non-power-of-two
patterns, causing unit tests for `olMemFill` to fail when run on L0.

This PR adds fallbacks in L0 plugin's `memoryFill` implementation to
support arbitrary pattern sizes:
- if all pattern bytes are the same, substitute `1` for `patternSize`
and proceed with the native fill
- if memory is host-accessible (host or shared alloc), then simply
`std::copy_n` the pattern
- if memory is device-only, upload a seed to the device, and
`memoryCopy` O(log n) times, doubling the pattern each time, until the
entire region is filled. The seed is the input pattern, but extended on
the host to 1-2KiB to potentially eliminate several small `memoryCopy`
calls that would otherwise be almost pure overhead.

Conceptually, this approach has better worst-case overhead than the one
found in the CUDA plugin (decompose the pattern to then run multiple
strided memsets) and the AMDGPU one (call `pushMemoryCopyH2DAsync` with
the pattern, setting `NumTimes`). Aligning the fallback fill approaches
is outside the scope of this PR, however - the main intent is to fix the
unit test failures.
https://invent.kde.org/qt/clang/llvm/-/commit/d90634dc185da79a8eb6a993c28614f4788e368e

Git commit a8ffce42477c909908d6f45511a48fd01a24837d by GitHub (on behalf of Younan Zhang) on 20/07/2026 at 11:32..
[Clang] Fix evaluation of fold expanded constraints for NTTP (#210005)

This is a rework of #200185 and also reflects what we did for TTP in
C++26 fold expression constraints (adc64c6e1745)

Fixes https://github.com/llvm/llvm-project/issues/199569
https://invent.kde.org/qt/clang/llvm/-/commit/a8ffce42477c909908d6f45511a48fd01a24837d

Git commit 14f6b9f0a3976f85d3ef509c8361991ae3702002 by GitHub (on behalf of Deepak Shirke) on 20/07/2026 at 11:35..
[VectorCombine] Fold bitcast(bitreverse.v8i8(bitcast(IntTy))) into bswap+bitreverse (#209037)

Add reverse direction to `foldBitOrderReverseAndSwap`:
`bitcast(bitreverse(<N x i8>)(bitcast(IntTy X)))` -->
`bitreverse(bswap(X))`

This avoids GPR<=>vector register crossings when integer ops are
cheaper. On AArch64 for example:

Before:
```asm
  fmov    d0, x0        ; GPR → vector crossing
  rbit    v0.8b, v0.8b
  fmov    x0, d0        ; vector → GPR crossing
```
After:
```asm
  rev     x8, x0        ; stays in integer registers
  rbit    x0, x8
```
The fold is cost-model driven and only fires when the integer version is
cheaper, so targets like X86+GFNI that prefer the vector form (single
`vgf2p8affineqb` instruction) are unaffected.

A new call site for `BitCast` instructions is added alongside the
existing `Call` instruction call site in the dispatch loop.

Fixes #201760
https://invent.kde.org/qt/clang/llvm/-/commit/14f6b9f0a3976f85d3ef509c8361991ae3702002

Git commit 06e3180cd141d9a8efdb9e9867b4a32300679038 by GitHub (on behalf of Barbara Mitic) on 20/07/2026 at 11:37..
[AMDGPU] Accept extractelement of a widening cast when folding image ops to a16 (#208207)

canSafelyConvertTo16Bit() recognizes a scalar coordinate that is a
direct sext/zext/fpext from a 16-bit value (sext gated on AllowI16SExt).
Per-dimension coordinates can instead arrive as an extractelement of a
widening vector cast (extractelement((s|z|fp)ext <N x i16/half> Vec),
Idx). When the cast has more than one use, the extractelement(cast) ->
cast(extractelement) canonicalization does not fire, so the cast is left
in place and the coordinate is not recognized.

Strip a leading extractelement before the cast check so the same logic
handles scalar and per-lane coordinates, and mirror this in
convertTo16Bit() by re-extracting from the narrow vector, allowing the
widening cast to be removed once it has no other uses.
https://invent.kde.org/qt/clang/llvm/-/commit/06e3180cd141d9a8efdb9e9867b4a32300679038

Git commit bd38dd0ace19c3b9512da2b37bb9690ee6c9e97f by GitHub (on behalf of AntonyCJ30) on 20/07/2026 at 11:39..
[X86] Fix swapped VPTERNLOG231_imm8/VPTERNLOG312_imm8 SDNodeXForm bodies (#209782)

Fixes #157929

VPTERNLOG231_imm8 and VPTERNLOG312_imm8 had their bodies swapped,
causing ISel to emit the wrong truth-table immediate whenever operand
reordering was needed (-O1+, not -O0).

Test changes:
- **avx512-vpternlog-commute.ll: regenerated with
update_llc_test_checks.py**
  (accounts for the large diff)
- Added 4 new cases: vpternlog231_rmik, vpternlog312_rmik,
  vpternlog231_rmbik, vpternlog312_rmbik

Tested: llvm-lit on llvm/test/CodeGen/X86 (no regressions), original
repro verified correct at -O0 through -O3, -Os, -Oz.
https://invent.kde.org/qt/clang/llvm/-/commit/bd38dd0ace19c3b9512da2b37bb9690ee6c9e97f

Git commit 60f8b4624badab6bec5e2600d82cf98b6a4e303b by GitHub (on behalf of Petar Avramovic) on 20/07/2026 at 11:40..
AMDGPU/GlobalISel: Fix G_MERGE_VALUES lowering for extended LLTs (#209202)

Use integer type for bit twiddling instead of scalar.
https://invent.kde.org/qt/clang/llvm/-/commit/60f8b4624badab6bec5e2600d82cf98b6a4e303b

Git commit 648aec12e5e5242c93aa73a21714553c6341ddc3 by GitHub (on behalf of Sander de Smalen) on 20/07/2026 at 11:50..
[AArch64] NFC: Factor out code from FP_TO_INT (SVE). (#207200)

This just moves out some of the SVE lowering code from
LowerVectorFP_TO_INT into a separate function, so that we can reuse that
in LowerVectorFP_TO_INT_SAT.
https://invent.kde.org/qt/clang/llvm/-/commit/648aec12e5e5242c93aa73a21714553c6341ddc3

Git commit 25b75a1e41c5fe71ed1f832c36c8bfb1bca1ab35 by GitHub (on behalf of Petar Avramovic) on 20/07/2026 at 11:51..
AMDGPU/GlobalISel: Stop using changeTo in legalizer actions (#209203)

Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
https://invent.kde.org/qt/clang/llvm/-/commit/25b75a1e41c5fe71ed1f832c36c8bfb1bca1ab35

Git commit 8abc26930cf9ee0f059228acdbd1d22cd1c325e3 by GitHub (on behalf of Simon Pilgrim) on 20/07/2026 at 12:04..
[X86] combineShiftRightLogical - fold srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction (#210281)

VectorCombine may have folded:
  icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1)

which DAG folds to:
  srl(vecreduce_umax(x),bw-1).

This match attempts to lower:
  srl(vecreduce_umax(x),bw-1) --> icmp_ne(movmsk(x),0) "any_of negative"
  srl(not(vecreduce_umax(x)),bw-1) --> icmp_eq(movmsk(x),0) "none_of negative"

The correct fix would be to improve vecreduce_or costs to prevent
VectorCombine doing this, but that change is far too big to be merged
into 23.x - so I've created the narrow backend fix.

Fixes #209714
https://invent.kde.org/qt/clang/llvm/-/commit/8abc26930cf9ee0f059228acdbd1d22cd1c325e3

Git commit d9c88062ecf9dc8ece4bb1482b0f1789979e3da5 by GitHub (on behalf of rdevshp) on 20/07/2026 at 12:05..
[analyzer] Fix _BitInt support & casting behavior for Z3 symbolic execution (#210525)

Forces symbolic cast to be enabled for z3 symbolic execution, and
switches away from Ctx.getTypeSize for getting the bit width of integral
types.

The current patch might be a bit problematic for z3 cross-check, as this
relies on symbolic integer cast to be always on. I am not sure if
turning on ShouldSupportSymbolicIntegerCasts would cause issues for the
supported range-based solver, so I only kept it turned on when
AnalysisConstraintsOpt == Z3ConstraintsModel.

Assisted-by: Codex
https://invent.kde.org/qt/clang/llvm/-/commit/d9c88062ecf9dc8ece4bb1482b0f1789979e3da5

Git commit 27fe16dcf920c92bcb7050e5abf4164ed3b496d1 by GitHub (on behalf of Dan Blackwell) on 20/07/2026 at 12:06..
[Darwin][ASan] Strip MTE-tags for inlined shadow translations (#204827)

https://github.com/llvm/llvm-project/pull/166453 stripped these tags
when the runtime performed the mem-to-shadow translation, but did not
account for ASan's inline translations. When an MTE-tagged address gets
translated, the tag bits are right-shifted too, resulting in a very high
address that faults when accessed.

This patch strips the MTE-tag bits before applying the translation on
Apple platforms.

rdar://180032780
https://invent.kde.org/qt/clang/llvm/-/commit/27fe16dcf920c92bcb7050e5abf4164ed3b496d1

Git commit 1caf9e1ef68ef85f1976e82bfc33befe1edc6eff by GitHub (on behalf of Federico Bruzzone) on 20/07/2026 at 12:09..
[mlir][ArmSVE] Fix comment inconsistency for `pack_lhs` in `ArmSVE/pack-unpack-mmt4d.mlir` (NFC) (#210502)

This PR simply fix a comment inconsistency for `pack_lhs` in
[ArmSVE/pack-unpack-mmt4d.mlir](https://github.com/llvm/llvm-project/compare/main...FedericoBruzzone:nfc-armsve?expand=1#diff-7be071860c440806b8dad954ed61946e7e9f27e032ed6044a704f0c0f70e4407)
as identified in #208226.

Signed-off-by: Federico Bruzzone <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/1caf9e1ef68ef85f1976e82bfc33befe1edc6eff

Git commit c30b1fa7a08e36346f80b1798ae587bc1d5e032b by GitHub (on behalf of Nico Weber) on 20/07/2026 at 12:09..
[gn build] Port b21fb937f165 (#210698)
https://invent.kde.org/qt/clang/llvm/-/commit/c30b1fa7a08e36346f80b1798ae587bc1d5e032b

Git commit 2cdd343022d4c5848281f4bb3670213f535884a2 by GitHub (on behalf of Petar Avramovic) on 20/07/2026 at 12:12..
AMDGPU/GlobalISel: Fix legalizer lowering for G_EXTRACT/INSERT_VECTOR_ELT (#210094)

Use LLT::integer in bit twiddling lowering for extract/insert vector element.
https://invent.kde.org/qt/clang/llvm/-/commit/2cdd343022d4c5848281f4bb3670213f535884a2

Git commit ca276b4822b1c748aaf9ef631d887143cb03a217 by GitHub (on behalf of Pengcheng Wang) on 20/07/2026 at 12:14..
[ExpandMemCmp][RISCV] Expand memcmp/bcmp for aligned pointers on strict-align targets (#209738)

`RISCVTTIImpl::enableMemCmpExpansion` previously disabled `memcmp`/`bcmp`
expansion whenever the target lacks unaligned scalar memory access. This is
too conservative: when both pointers are statically known to be
sufficiently aligned (e.g. `bcmp(ptr align 8, ptr align 8, 32)`), only
naturally aligned loads are needed, which are fine on strict-align
targets.

`ExpandMemCmp` now keeps a candidate load size only if, given the known
common alignment of the two pointers, the access is naturally aligned or
the target reports it via `allowsMisalignedMemoryAccesses`; otherwise it
falls back to the libcall. The query tests whether the access is
*allowed* (not *fast*), so it is a no-op for targets that already allow
unaligned access (X86, AArch64, ...).

The known alignment now also folds in the `align` attributes on the call
arguments (`CallBase::getParamAlign`), not just the pointer value.

RISCV drops the early return and only offers overlapping loads / tail
expansions when unaligned scalar access is supported.

Fixes #209511.

Assisted-by: TRAE CLI (DeepSeek V4 Pro)
https://invent.kde.org/qt/clang/llvm/-/commit/ca276b4822b1c748aaf9ef631d887143cb03a217

Git commit 0000fd1fc63dcc7f0fe87091fe2e5a0daf5ec727 by GitHub (on behalf of Simon Pilgrim) on 20/07/2026 at 12:19..
[VectorCombine] load-widening.ll - add test coverage for all 4 x86-64 cpu levels and aarch64 endian test coverage (#210690)

Removed x86 endianess tests which makes no sense (and are likely to misbehave) and add equivalent test coverage to aarch64

Noticed while reviewing #209775
https://invent.kde.org/qt/clang/llvm/-/commit/0000fd1fc63dcc7f0fe87091fe2e5a0daf5ec727

Git commit ac41c58f7b3b26a4bd4260d05afd7c3b2ccc3c72 by GitHub (on behalf of BohdanYehorov) on 20/07/2026 at 12:20..
[clang][docs] Fix include path in InternalsManual (#209458)

The paths `include/Basic/StmtNodes.td` and `include/AST/Expr*.h` in the
Clang Internals Manual are incorrect.
https://invent.kde.org/qt/clang/llvm/-/commit/ac41c58f7b3b26a4bd4260d05afd7c3b2ccc3c72

Git commit a35bcaef8c1a0867af4c3b547422b4783c88fc96 by GitHub (on behalf of Petar Avramovic) on 20/07/2026 at 12:24..
AMDGPU/GlobalISel: Explicitly widen scalar to i32 for load and store (#210095)

Affects f16 and bf16. Earlier, they were widened to f32 and s32 respectively.
The actual error was the artifact combiner creating a copy between f32/i32
which fails in the machine verifier. Maybe we could create a bitcast there.
However i32 is more efficient for us and matches well with how argument
lowering keeps f16 and bf16 in i32 copies to/from physical registers.
Also starting from f16 store, G_STORE %0(f16), %1(p1) :: (store (f16),
and doing widen scalar to 32 bit type, i32 makes more sense since store
will store 16 least significant bits G_STORE %0(i32), %1(p1) :: (store (f16)
compared to G_STORE %0(f32), %1(p1) :: (store (f16), which looks incorrect if
we assume input was really in f32 format.
https://invent.kde.org/qt/clang/llvm/-/commit/a35bcaef8c1a0867af4c3b547422b4783c88fc96

Git commit fc6fa9a27419fb065b960f842f6d1f0c7a69e823 by Mariusz Sikora on 20/07/2026 at 13:06..
[AMDGPU] Builtins and intrinsics for v_cvt_scalef32_pk32_(fp|bf)6_f32

- builtins with documentation
- instructions
- new subtarget feature only for gfx13
- GlobalISel RegBankLegalize rules
- tests
https://invent.kde.org/qt/clang/llvm/-/commit/fc6fa9a27419fb065b960f842f6d1f0c7a69e823