[qt/clang/llvm]: Summary of bulk changes made

KDE Git Services - Bulk Change <[email protected]> Wed, 22 Jul 2026 18:12:56 +0000 (UTC)

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Git repository change summary for qt/clang/llvm
Pushed by mirror-service into branch 'upstream/users/jerryyin/amdgpu-hoist-uniform-readfirstlane'.
Changed from 0000000000000000000000000000000000000000 to db4972674de235fc71a3ae0c8da60d0f219bfacd
Acknowledgement was received that this change introduces only existing code that has been pushed to another public open source repository.

This change contains the following new commits:

Git commit 77e29dd5968dbd67b2f299d604a940b0b42a8111 by proaditya on 05/02/2026 at 22:41..
[AMDGPU] Add static performance simulator for gfx1250 kernels

Introduces GPUCompilerSim, a MachineFunctionPass that estimates kernel
performance without hardware. Runs before MC lowering and emits results
as assembly comments, debug logs, or JSON/YAML for CI.

Goals:
- Enable performance decisions across the stack (Triton, compiler, kernels)
without hardware access
- Rapid iteration: immediate feedback on stalls, IPC, resource utilization
- Identify optimizations invisible in source (bank conflicts, co-exec misses)
- Prototype HW features: evaluate parameters before silicon

Quick Start:
# Enable via environment variable
export AMDGPU_ENABLE_STATIC_SIM=1
llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 kernel.ll -o kernel.s
# Or run triton kernel with above EV (or any flow that invokes LLVM backend)

# Or via command line flag
llc -amdgpu-enable-static-sim -mcpu=gfx1250 kernel.ll -o kernel.s

# Verbose per-instruction output
llc -amdgpu-enable-static-sim -amdgpu-static-sim-verbose ...

Features:
* Instruction Store Cache: 4-line circular buffer model with configurable
SQC-to-IS latency, steady-state stall prediction for loops
* Memory System: FIFO backpressure for DS/VMEM/SMEM/TDM, false wait detection,
per-op completion tracking with configurable latencies
* Register File: Scoreboard-based RAW hazard tracking (all inst types),
VGPR operand cache simulation, bank conflict detection with broadcast
deduplication, VA_VDST/VA_SSRC counter modeling
* WMMA Co-execution: Per-stage slot tracking (E0/E/I/V), WMMA_SCALE
decomposition (scale-read + XDL), configurable co-exec masks
* Control Flow: s_set_vgpr_msb fusion tracking, delay_alu consumption
* CFG Analysis: Loop-aware cold/warm iteration modeling, scaled metrics

Stall Categories:
FU (unit busy), WMMACoExec, DelayAlu, Wait (waitcnt), MemFIFO,
RegBank (bank conflict), ISFetch (instruction fetch), RAW (scoreboard)

Example Function Summary:
;; ============================================================
;; attn_fwd_kernel - STATIC PERFORMANCE ESTIMATE (gfx1250)
;; ============================================================
;;
;; === Scaled Metrics (loops x trip count) ===
;; Instructions: 72410
;; Cycles: 78729
;; Stall: 33662 cycles (42.8%)
;; FU:2592 | WMMACoExec:8247 | DelayAlu:4793 | Wait:15882 | RegBank:2009
;; WMMA windows: 17408 | Co-executed: 5444 (31%)
;;
;; === Instruction Breakdown (Raw / Scaled) ===
;; VALU: 6638/39281 | SALU: 533/2796 | TRANS: 1036/9096 | WMMA: 192/2176
;; DS_RD: 288/3264 | VMEM: 186/186 | Spill: 53/53 | Reload: 53/53
;;
;; === Derived Metrics ===
;; IPC: 0.68 | Stall ratio: 42.8%

Example Block Summary:
;=== Block (loop): Cold=1519cyc Warm=1519cyc Trip=32 Scaled=48608cyc ===
; VALU:1053 SALU:73 TRANS:260 WMMA:64 DS:96
; Stall: 371 cycles (24%) | FU:62 | WMMACoExec:242 | RegBank:49

GPUCompilerSim can also offer assembly instruction level insights with inline annotations
export AMDGPU_STATIC_SIM_INLINE=1 or -amdgpu-static-sim-inline

Example Inline Annotations
;Sim: 0EEIEEIIVV | Stall:1
v_wmma_scale_f32_16x16x128_f8f6f4 v[90:97], v[114:129], v[50:65], ...
;Sim: WMMA[1/10] E OK
s_or_b32 s6, s29, s23
;Sim: WMMA[2/10] E OK
s_mulk_i32 s14, 0x2200
;Sim: Fused
s_set_vgpr_msb 0xc002
;Sim: WMMA[6/10] I BLOCKED | Stall:1
v_pk_add_f32 v[138:139], v[134:135], v[238:239]
;Sim: WMMA[8/10] V BLOCKED | Stall:2
v_cvt_scalef32_pk8_fp8_f32 v[244:245], v[26:33], 1.0
https://invent.kde.org/qt/clang/llvm/-/commit/77e29dd5968dbd67b2f299d604a940b0b42a8111

Git commit 0abae06b7f6cfda0238c35bd7af4e711c2a0e7f0 by proaditya on 11/02/2026 at 02:16..
Print warm block metrics only
https://invent.kde.org/qt/clang/llvm/-/commit/0abae06b7f6cfda0238c35bd7af4e711c2a0e7f0

Git commit 780186c667cef2d843cc26e45cdda1ac01d9da40 by proaditya on 11/02/2026 at 02:17..
Add JSON dumping with AMDGPU_GPU_CSIM_JSON=/path/to.json or -amdgpu-gpu-csim-json
https://invent.kde.org/qt/clang/llvm/-/commit/780186c667cef2d843cc26e45cdda1ac01d9da40

Git commit bd3aeadff5cf6e8b1e7d48d6f04d5c8b79e9e4bc by GitHub (on behalf of Kerbow, Austin) on 09/03/2026 at 03:52..
[AMDGPU] Add ML-oriented coexec scheduler selection and queue handling (#5422)

This patch adds the initial coexec scheduler scaffold for machine
learning workloads on gfx1250.

It introduces function and module-level controls for selecting the
AMDGPU preRA and postRA schedulers, including an `amdgpu-workload-type`
module flag that maps ML workloads to coexec preRA scheduling and a nop
postRA scheduler by default.

It also updates the coexec scheduler to use a simplified top-down
candidate selection path that considers both available and pending
queues through a single flow, setting up follow-on heuristic work.
https://invent.kde.org/qt/clang/llvm/-/commit/bd3aeadff5cf6e8b1e7d48d6f04d5c8b79e9e4bc

Git commit b9c13f96e1f7b835d96b129ef82fd31d895617bb by GitHub (on behalf of Kerbow, Austin) on 09/03/2026 at 04:20..
[AMDGPU] Add structural stall heuristic to scheduling strategies (#5423)

Implements a structural stall heuristic that considers both resource
hazards and latency constraints when selecting instructions. In coexec,
this changes the pending queue from a binary “not ready to issue”
distinction into part of a unified candidate comparison. Pending
instructions still identify structural stalls in the current cycle, but
they are now evaluated directly against available instructions by stall
cost, making the heuristics both more intuitive and more expressive.

- Add getStructuralStallCycles() to GCNSchedStrategy that computes the
number of cycles an instruction must wait due to:
- Resource conflicts on unbuffered resources (from the SchedModel)
- Sequence-dependent hazards (from GCNHazardRecognizer)

- Add getHazardWaitStates() to GCNHazardRecognizer that returns the
number
of wait states until all hazards for an instruction are resolved,
providing cycle-accurate hazard information for scheduling heuristics.
https://invent.kde.org/qt/clang/llvm/-/commit/b9c13f96e1f7b835d96b129ef82fd31d895617bb

Git commit e072334d42d380538e652af75971ed07c6a77352 by Austin Kerbow on 10/03/2026 at 00:49..
Merge main into GPUCompilerSim

Update to Triton llvm-hash: 20902f0b721ba6cf2fb134362d27144bd8584d53
https://invent.kde.org/qt/clang/llvm/-/commit/e072334d42d380538e652af75971ed07c6a77352

Git commit 004eacf10fa98a855525b21242abacef9118a4de by Austin Kerbow on 10/03/2026 at 01:15..
Merge main into CoExecScheduler

Update to Triton llvm-hash: 20902f0b721ba6cf2fb134362d27144bd8584d53
https://invent.kde.org/qt/clang/llvm/-/commit/004eacf10fa98a855525b21242abacef9118a4de

Git commit e5092da035de1299c5ef0c4379fe4c4f4eb2ea7a by Austin Kerbow on 10/03/2026 at 01:45..
Merge branch 'GPUCompilerSim' into CoExecScheduler
https://invent.kde.org/qt/clang/llvm/-/commit/e5092da035de1299c5ef0c4379fe4c4f4eb2ea7a

Git commit e497d90e592336c2927b6fbbbf6c9b67f37d657c by Austin Kerbow on 10/03/2026 at 20:36..
[AMDGPU] Remove dead code in SIInstrInfo::getRepeatRate. NFC
https://invent.kde.org/qt/clang/llvm/-/commit/e497d90e592336c2927b6fbbbf6c9b67f37d657c

Git commit eb156ac4482515efe0aabca622bbaeb2b83452d7 by GitHub (on behalf of Kerbow, Austin) on 10/03/2026 at 20:44..
Merge branch 'GPUCompilerSim' into CoExecScheduler (#5534)
https://invent.kde.org/qt/clang/llvm/-/commit/eb156ac4482515efe0aabca622bbaeb2b83452d7

Git commit 4645ba68df7898d3ab1393914b7ccc6dcdaea8e1 by Austin Kerbow on 23/03/2026 at 17:27..
Merge main into CoExecScheduler

Update to Triton llvm-hash: 7f77ca0dbda4abbf9af06537b2c475f20ccd6007
https://invent.kde.org/qt/clang/llvm/-/commit/4645ba68df7898d3ab1393914b7ccc6dcdaea8e1

Git commit 7698f399414730c1748bb7668577c1938a2ff460 by GitHub (on behalf of Kerbow, Austin) on 31/03/2026 at 16:59..
Reapply "[AMDGPU] Add HWUI pressure heuristics to coexec strategy (#1… (#5764)
https://invent.kde.org/qt/clang/llvm/-/commit/7698f399414730c1748bb7668577c1938a2ff460

Git commit 7f11f78f67ab52ecb3b0c8ba2a81e7fbc784464b by Austin Kerbow on 24/04/2026 at 19:07..
Merge main into CoExecScheduler

Update to Triton llvm-hash: f0f96c7f788b90e48a6925437e918c3196913325

# Conflicts:
# llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
# llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
# llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
# llvm/lib/Target/AMDGPU/CMakeLists.txt
# llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
# llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
# llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
# llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
https://invent.kde.org/qt/clang/llvm/-/commit/7f11f78f67ab52ecb3b0c8ba2a81e7fbc784464b

Git commit 9211229b40fb4d17cd5669790dbba0c0b4739cef by Austin Kerbow on 26/04/2026 at 18:51..
[AMDGPU] Track VALU instructions separately for WMMA coexecution hazards

WMMA coexecution hazards can only be resolved by VALU instructions, not
S_NOPs. Track VALU/WMMA instructions separately so the scheduler can
accurately determine stall cycles.
https://invent.kde.org/qt/clang/llvm/-/commit/9211229b40fb4d17cd5669790dbba0c0b4739cef

Git commit 319cd03ea218ef23417f2e0ce4710c524463718b by Austin Kerbow on 26/04/2026 at 18:51..
[AMDGPU] Allow independent WMMA to resolve WMMA coexecution hazards
https://invent.kde.org/qt/clang/llvm/-/commit/319cd03ea218ef23417f2e0ce4710c524463718b

Git commit 6f3b1dcb3626e0faad7cf9f355feb4f838ba22d8 by Austin Kerbow on 26/04/2026 at 18:51..
[AMDGPU] Factor out WMMA co-execution types to shared header. NFC

Create AMDGPUCoExecInfo.h with shared co-execution slot infrastructure.

This enables sharing co-execution modeling between AMDGPUStaticSimulator
and other passes like GCNHazardRecognizer and the schedulers.
https://invent.kde.org/qt/clang/llvm/-/commit/6f3b1dcb3626e0faad7cf9f355feb4f838ba22d8

Git commit 64a34d94c061d5d4618a2304789afe5ebaab3c48 by Austin Kerbow on 26/04/2026 at 18:51..
[AMDGPU] Add InstructionFlavor and slot preferences to CoExecInfo. NFC

Extend the shared co-execution header with instruction flavors
and slot preferences utils.

This enables schedulers to make position-aware slot decisions.
https://invent.kde.org/qt/clang/llvm/-/commit/64a34d94c061d5d4618a2304789afe5ebaab3c48

Git commit 969e4f6821795d22a5c9b213325e43f7f8857d7c by Austin Kerbow on 26/04/2026 at 18:51..
[AMDGPU] Update XDL WMMA latency

Update the scheduling model to correct values.

Fix the F8F6F4 SchedWriteVariant predicate: the old PredIsF8_WMMA_SCALE
only checked <= MATRIX_FMT_BF8 and missed F6/BF6 inputs. Rename to
PredIsNotBothF4_WMMA_SCALE and check != MATRIX_FMT_FP4.
https://invent.kde.org/qt/clang/llvm/-/commit/969e4f6821795d22a5c9b213325e43f7f8857d7c

Git commit 7d85aff1c24dd6d4b1eebcbb42501be41c878f03 by Austin Kerbow on 26/04/2026 at 18:51..
[AMDGPU] Add WMMA coexec tracking to GCNHazardRecognizer

Extend GCNHazardRecognizer with a pre-RA operating mode that tracks WMMA
co-execution windows during scheduling.

Replace the boolean IsHazardRecognizerMode with a three-way OperatingMode
enum (PreRA, PostRA, HazardRecognizerMode). The co-exec scheduling
strategy installs a PreRA-mode hazard recognizer that enforces WMMA
co-execution slot constraints, TRANS back-to-back hazards, and
multi-cycle VALU pipeline occupancy. The PostRA scheduler also uses this
tracking so that post-RA scheduling respects the same constraints.
https://invent.kde.org/qt/clang/llvm/-/commit/7d85aff1c24dd6d4b1eebcbb42501be41c878f03

Git commit e8bcabdf514c5e3e3b70399a6df2c94965fe1c21 by Austin Kerbow (on behalf of mssefat) on 26/04/2026 at 18:51..
[AMDGPU] Add anti-hint to avoid WMMA hazards on gfx1250
https://invent.kde.org/qt/clang/llvm/-/commit/e8bcabdf514c5e3e3b70399a6df2c94965fe1c21

Git commit bf7e65088c2bc0cff1105c883c8b94d1ac345626 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:51..
[AMDGPU] Extend gfx1250 anti-hints to cover TRANs hazads
https://invent.kde.org/qt/clang/llvm/-/commit/bf7e65088c2bc0cff1105c883c8b94d1ac345626

Git commit 1c5537a5487ca2e64ca7a670d463d84f571b79cf by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:51..
[AMDGPU] Add gfx1250 anti-hints for va_vdst WAR hazards
https://invent.kde.org/qt/clang/llvm/-/commit/1c5537a5487ca2e64ca7a670d463d84f571b79cf

Git commit 4171b453f148d9461d53fd1dbdceab45bc4fcc29 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:52..
[AMDGPU] Add stalls between VALU with SGPR use/def and SALU instructions
https://invent.kde.org/qt/clang/llvm/-/commit/4171b453f148d9461d53fd1dbdceab45bc4fcc29

Git commit d0fac9aade4e4978a421b958fda3433ef8a5bb14 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:54..
Add repeat rate test

Change-Id: Ideb0ab2d13ed4e4d7c98a79c920dfdc4819b8ed6
https://invent.kde.org/qt/clang/llvm/-/commit/d0fac9aade4e4978a421b958fda3433ef8a5bb14

Git commit 3b8282d4018988f27bfbf3ed08610231cc8019a9 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:54..
[MISched] Add repeat rate to block buffered resources

Change-Id: I0d75ebc2366cfd67b9ba96f9de3f1d2dc3599d63
https://invent.kde.org/qt/clang/llvm/-/commit/3b8282d4018988f27bfbf3ed08610231cc8019a9

Git commit 53d0e734a8bf68fb43153c5b16288ae624f0c72e by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:55..
[AMDGPU] Add overrides to control LDS instruction latency
https://invent.kde.org/qt/clang/llvm/-/commit/53d0e734a8bf68fb43153c5b16288ae624f0c72e

Git commit 80f5fbed89ed9dc47833757eb2a0db90b631f5ab by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 18:55..
[AMDGPU] Add flag to control maximum RP during scheduling
https://invent.kde.org/qt/clang/llvm/-/commit/80f5fbed89ed9dc47833757eb2a0db90b631f5ab

Git commit 1ca27faf44cc47a0dcd0ebaf51be1d04e9141a1b by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:48..
[AMDGPU] Add stalls for DS FIFO buffer

Change-Id: I73e56da97a931349e0655e4e20b24aeb97920647
https://invent.kde.org/qt/clang/llvm/-/commit/1ca27faf44cc47a0dcd0ebaf51be1d04e9141a1b

Git commit cc62dc8b75e174387632d6229d82a5f96dab0c53 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:48..
Typo

Change-Id: I8b8da8a07be84506483f474d0a5e10ad79178c15
https://invent.kde.org/qt/clang/llvm/-/commit/cc62dc8b75e174387632d6229d82a5f96dab0c53

Git commit e03394ee605d8f548d48f320c66d0774359a46ab by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:48..
Claude Code review

Change-Id: Id4983ca59270c8bb2d261d38a6e7f2483c9d237e
https://invent.kde.org/qt/clang/llvm/-/commit/e03394ee605d8f548d48f320c66d0774359a46ab

Git commit 2666eac446c9d85e6fe68a8596706cea6e044730 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:51..
[AMDGPU] Add block carried latency to CoExecSched

Change-Id: Ib04e40e57d38e127d6c5452d1719e32dacef2ade
https://invent.kde.org/qt/clang/llvm/-/commit/2666eac446c9d85e6fe68a8596706cea6e044730

Git commit e57506c9839d1d77da406867f1d84942d520aa10 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:52..
Claude Code review

Change-Id: Iab06de2981b27667cc29a56931dd378ecf7a1b0c
https://invent.kde.org/qt/clang/llvm/-/commit/e57506c9839d1d77da406867f1d84942d520aa10

Git commit dd6d4cd1ada581972b7c7176d7c2c98e35fda785 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:53..
Formatting

Change-Id: I3d89fba145471141ef945b1de15330caa245e82d
https://invent.kde.org/qt/clang/llvm/-/commit/dd6d4cd1ada581972b7c7176d7c2c98e35fda785

Git commit eb0ecb26b7b9f16a2c323b0bf18eee594d45f633 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:53..
Merge conflict

Change-Id: I24f471688f9d0604b45e95a4fa4da85fb0d9ed76
https://invent.kde.org/qt/clang/llvm/-/commit/eb0ecb26b7b9f16a2c323b0bf18eee594d45f633

Git commit 8637b92be8d5053c29657c7d9a582ac5af07261b by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:55..
[AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5
https://invent.kde.org/qt/clang/llvm/-/commit/8637b92be8d5053c29657c7d9a582ac5af07261b

Git commit 6bd25d9f3ad93192476d6255c289820d66c48472 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:55..
Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484
https://invent.kde.org/qt/clang/llvm/-/commit/6bd25d9f3ad93192476d6255c289820d66c48472

Git commit 62078cd9f53ee66fafa1c3fb9e3c9a8609ccb180 by Austin Kerbow (on behalf of Jeffrey Byrnes) on 26/04/2026 at 19:55..
Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f
https://invent.kde.org/qt/clang/llvm/-/commit/62078cd9f53ee66fafa1c3fb9e3c9a8609ccb180

Git commit 3ac9070529e17130a42b6569ad53f479deecf718 by Austin Kerbow on 28/04/2026 at 18:42..
[AMDGPU] Add ShadowMix heuristic with template-derived coexec demand

Adds the ShadowMix scheduling heuristic to the coexec strategy. ShadowMix
defers compatible filler instructions (VALU/SALU/DS/VMEM/TRANS) so they
land inside the shadow of a multi-cycle window producer (WMMA, TRANS,
MultiCycleVALU) rather than executing outside any shadow.

The heuristic is template-derived rather than rule-based: filler demand
(I-slots, E-slots) is computed per-window from each WMMA's CoExecInfo
template, not from hardcoded constants. A region-aggregate demand serves
as the fallback when no producer is present in the candidate pair.

Three layers, applied in order:
1. Producer over compatible filler — never schedule a filler before its
producer, since that wastes the slot.
2. Enablement when demand unsatisfied — prefer non-producers that
directly enable, or are on a BFS path to, the most deficient filler
flavor.
3. Producer promotion when demand satisfied — once enough fillers are
ready, promote the producer so the window opens.

Adds RegionMixInfo (per-flavor ready/unavailable/scheduled counts) and
WindowSlotDemand (template-derived slot counts) as supporting structures.
Generalizes producer detection from WMMA-only to any HardwareUnit with
producesCoexecWindow() set, covering MultiCycleVALU (CVT) and TRANS.

Includes test coverage in coexec-sched-shadow-mix.mir demonstrating the
behavioral difference between coexec and default scheduling.
https://invent.kde.org/qt/clang/llvm/-/commit/3ac9070529e17130a42b6569ad53f479deecf718

Git commit cb1ee98653c16242518b2da63d3bcd63fd37b8cb by Austin Kerbow on 28/04/2026 at 18:43..
[AMDGPU] Add CoexecWindow lifecycle and two-window state machine

Adds CoexecWindow tracking to the coexec scheduling strategy. Each window
is a co-execution window produced by a multi-cycle instruction (WMMA,
TRANS, MultiCycleVALU). The window goes through a lifecycle:

Unpopulated → Populated (demand computed from CoExecInfo template)
→ Active (producer scheduled, StartCycle/EndCycle set)
→ Expired (TopReadyCycle >= EndCycle → rotate)

The strategy maintains two windows: CurrentWindow and NextWindow. While
CurrentWindow is active and its filler demand is satisfied, ShadowMix
switches to NextWindow as the target so the scheduler prepares fillers
for the upcoming producer in parallel with the current one executing.
This is the lookahead path for back-to-back producers.

Window demand is derived from the producer's WindowSlotDemand template
rather than hardcoded counts. populate() picks the best producer in the
region by HardwareUnit pressure; activate() sets the cycle bounds when
the producer is scheduled; isExpired() drives rotation in
updateForScheduling().
https://invent.kde.org/qt/clang/llvm/-/commit/cb1ee98653c16242518b2da63d3bcd63fd37b8cb

Git commit 8926f84e070439716b1b521e02d30970fc9b9e94 by Austin Kerbow on 28/04/2026 at 18:44..
[AMDGPU] Add roofline co-execution analysis for scheduling regions

Computes a region-level upper bound on the number of WMMA co-exec slots
that can be filled by the available consumer instructions, using a
bipartite max-flow (Edmonds-Karp) on aggregated consumer classes vs slot
types. Yields LowerBoundStalls = TotalSlots - MaxFilledSlots — an exact
lower bound on unavoidable stall cycles under arbitrary reordering.

The result is exposed via getRooflineResult() and dumped under
-debug-only=machine-scheduler. No scheduling decisions consume it yet;
follow-up patches can use it to bound deferral aggressiveness or to
disable ShadowMix when LowerBoundStalls indicates no exposed work.
https://invent.kde.org/qt/clang/llvm/-/commit/8926f84e070439716b1b521e02d30970fc9b9e94

Git commit 4901e75e027115b067d4ba11cb1e96030adc503d by Austin Kerbow (on behalf of Jeffrey Byrnes) on 28/04/2026 at 18:44..
[AMDGPU] Add tryCoexecSlot to honor preferences / avoidances.
https://invent.kde.org/qt/clang/llvm/-/commit/4901e75e027115b067d4ba11cb1e96030adc503d

Git commit 605ea4f2f9d8db141ec2933a05ee8eb6ea756163 by Austin Kerbow on 28/04/2026 at 18:44..
[AMDGPU] Model VaVdst-ordered XDL WMMA/SWMMAC writes in SIInsertWaitcnts

32-bit accumulator XDL instructions (WMMA/SWMMAC with F32/I32 results) act as
a fence: when they signal done on the shared done bus, all previously issued
VALU results across all pipes (CSMACC, TRANS, DPMACC) are guaranteed to have
been written back. This allows the wait insertion pass to compute relaxed
(non-zero) va_vdst values instead of the conservative wait(0) used when
multiple out-of-order event types are pending.

Add VGPR_XDL_ORDERED_WRITE event type to distinguish 32-bit XDL from
unordered 16-bit XDL. When a 32-bit XDL is encountered, promote pending
VA_VDST register scores to the XDL's score and clear prior out-of-order
event types. Track LastXDLOrderedVAVDSTScore to prevent re-promoting scores
already collapsed by a prior fence.
https://invent.kde.org/qt/clang/llvm/-/commit/605ea4f2f9d8db141ec2933a05ee8eb6ea756163

Git commit 27583c3935696633d43dac97c2e3053912ad1685 by Austin Kerbow on 28/04/2026 at 18:44..
[AMDGPU] Set Policy.ShouldTrackLaneMasks = True for CoExecSchedStrategy
https://invent.kde.org/qt/clang/llvm/-/commit/27583c3935696633d43dac97c2e3053912ad1685

Git commit c865826a86a49969220b119e44537324bcbcc201 by Austin Kerbow on 28/04/2026 at 18:44..
Revert "[AMDGPU] Improve max3/min3 formation for tree-structured reductions (#190734)"

This reverts commit d6d99d9f600fc54bc9d0ee47e3130953372c56d5.
https://invent.kde.org/qt/clang/llvm/-/commit/c865826a86a49969220b119e44537324bcbcc201

Git commit 9ef8835cd7b209b93af05b953915296c430cb559 by Jeffrey Byrnes on 29/04/2026 at 00:31..
[AMDGPU] Do not add unnecessary latency for dependencies
https://invent.kde.org/qt/clang/llvm/-/commit/9ef8835cd7b209b93af05b953915296c430cb559

Git commit a26cc0c4f21ba162ac8c2bb0337eb33ba7c7ba30 by Austin Kerbow on 29/04/2026 at 03:15..
[AMDGPU] Enable HazardRec in getStructuralStallCycles
https://invent.kde.org/qt/clang/llvm/-/commit/a26cc0c4f21ba162ac8c2bb0337eb33ba7c7ba30

Git commit 6dd769274f61c23cc384c0877974bd96635a6731 by Austin Kerbow on 29/04/2026 at 03:41..
[AMDGPU] Add exposed-cycle priority sort to coexec scheduler

Adds an optional per-HardwareUnit "remaining exposed cycles" estimate
that the critical-resource sort can use to prioritize HWUIs whose
work is least likely to fit inside a coexec window. Disabled by
default; opt in via -amdgpu-coexec-exposed-sort=greedy|roofline.

greedy - hand-ordered allocation: WMMA E/I-slots are first claimed
by DS, then SALU, then TRANS, then SingleCycleVALU; any
remainder goes into MultiVALU shadow. Mirrors the prior
PipelinedScheduler heuristic, including the DSBound guard
which leaves all exposed counts at 0 for DS-bound regions.
roofline - per-class flow recovered from the existing TinyMaxFlow
solution; covers every flavor mapped by flavorToCoExecMask
(greedy's 6 flavors plus VMEM and DMA).

The sort gives non-zero-exposed flavors priority over zero-exposed
ones, then sorts by raw remaining-exposed count. Counters decrement
on schedule when the SU is not currently inside an active CoexecWindow
(producers always decrement). Exposed counts are dumped in the
per-region debug summary when the flag is on.
https://invent.kde.org/qt/clang/llvm/-/commit/6dd769274f61c23cc384c0877974bd96635a6731

Git commit f7b1f759b47096fb719197365279ed326745d284 by Austin Kerbow on 29/04/2026 at 04:02..
[AMDGPU] BarrierLatency: tolerate non-TENSOR_CNT preds of S_WAIT_TENSORCNT

The S_WAIT_TENSORCNT handler asserted that every predecessor with a
data dependency on the TENSORcnt pseudo-register also carries the
TENSOR_CNT TSFlag. In practice the dep can flow through an intervening
SU that is not itself a tensor-load (e.g. a COPY or other pseudo), so
the assertion fires.

Skip such predecessors instead — they are not in OutstandingTDM, so
needWaitFor cannot reason about them and the surrounding logic has
nothing useful to do here. Fixes the post-RA scheduler crash on
kernels that route TENSORcnt deps through non-tensor SUs.
https://invent.kde.org/qt/clang/llvm/-/commit/f7b1f759b47096fb719197365279ed326745d284

Git commit 4b1488866ec573cd1e8a9de37a6aea335c3bf592 by Austin Kerbow on 29/04/2026 at 04:51..
[AMDGPU] HazardRec: block VALU-pipe instrs in MultiCycleVALU shadow

A multi-cycle VALU (e.g. CVT with RepeatRate>1) holds the VALU pipe
for RepeatRate cycles. Anything else that needs the VALU pipe -- VALU,
WMMA, SWMMAC, TRANS -- cannot coexecute and must stall. Only off-pipe
instructions (MEM, SALU, control) can fill the shadow.

The previous logic stalled subsequent single-cycle VALU but explicitly
let WMMA/SWMMAC/TRANS through, which is the inverse of the actual
pipe constraint. Invert the test: stall any VALU-pipe instruction,
let everything else pass.
https://invent.kde.org/qt/clang/llvm/-/commit/4b1488866ec573cd1e8a9de37a6aea335c3bf592

Git commit 9b2b47ff56d6bbbf691d0be3b98193720a40f4d3 by Jeffrey Byrnes on 30/04/2026 at 16:11..
[AMDGPU] Add BarrierLatency mutation to CoExec scheduler

The CoExec scheduler was missing critical DAG mutations that are added
to other schedulers like the MaxOccupancy scheduler. This fix adds:
- Barrier latency mutation (critical for signal-wait latency)

Co-Authored-By: Claude Opus 4 <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/9b2b47ff56d6bbbf691d0be3b98193720a40f4d3

Git commit 72f7de912c3d3c4f7de8de4846d5efe30fd7fbf0 by Austin Kerbow on 30/04/2026 at 16:28..
[AMDGPU] Select nop postRA scheduler with coexec
https://invent.kde.org/qt/clang/llvm/-/commit/72f7de912c3d3c4f7de8de4846d5efe30fd7fbf0

Git commit b2585797f0d3340f8180db1f77ae5b1c9490bd8b by Austin Kerbow on 30/04/2026 at 16:50..
[AMDGPU] Fix wrong SU in tryCoexecSlot
https://invent.kde.org/qt/clang/llvm/-/commit/b2585797f0d3340f8180db1f77ae5b1c9490bd8b

Git commit bc5d15d25ac210f82247c250593712bfe522a346 by Austin Kerbow on 30/04/2026 at 16:57..
[AMDGPU] Set default CoexecExposedMode to roofline
https://invent.kde.org/qt/clang/llvm/-/commit/bc5d15d25ac210f82247c250593712bfe522a346

Git commit be8db4a903507fa41d704f63879787929ad324b4 by Austin Kerbow on 30/04/2026 at 17:27..
[AMDGPU] Update DS FIFO size to align with GPUCompilerSim
https://invent.kde.org/qt/clang/llvm/-/commit/be8db4a903507fa41d704f63879787929ad324b4

Git commit 4ce5ca2e82aee4acc171a4676941765f39529848 by Austin Kerbow on 30/04/2026 at 17:34..
[AMDGPU] Fix multi-cycle VALU hazard checking
https://invent.kde.org/qt/clang/llvm/-/commit/4ce5ca2e82aee4acc171a4676941765f39529848

Git commit bb2e410d91d1139653485eb04e9096752ea0461c by Jeffrey Byrnes on 30/04/2026 at 18:13..
[AMDGPU] Ensure we cover latency before scheduling Memory Pipeline instructions
https://invent.kde.org/qt/clang/llvm/-/commit/bb2e410d91d1139653485eb04e9096752ea0461c

Git commit d8da4219f6ed4aa6e456616d0e1334cd3c902c8f by Jeffrey Byrnes on 30/04/2026 at 18:44..
[AMDGPU] Handle s_wait -> s_wait latency for tensorcnt edges
https://invent.kde.org/qt/clang/llvm/-/commit/d8da4219f6ed4aa6e456616d0e1334cd3c902c8f

Git commit 535bba8c810fdbfadc8ba048e4e13bf662ea6b24 by Jeffrey Byrnes on 30/04/2026 at 18:47..
[AMDGPU] VMEM instructions are VMEM flavor
https://invent.kde.org/qt/clang/llvm/-/commit/535bba8c810fdbfadc8ba048e4e13bf662ea6b24

Git commit 1418a03d3ca826f07ccaab7ccd907e02d0cc51a1 by Austin Kerbow on 30/04/2026 at 20:13..
[AMDGPU] Set default DS FIFO size to 16 to patch prototype
https://invent.kde.org/qt/clang/llvm/-/commit/1418a03d3ca826f07ccaab7ccd907e02d0cc51a1

Git commit 427cd8271e807a381365658b63bc5068edbc81ac by Austin Kerbow on 30/04/2026 at 20:13..
[AMDGPU] CoExec: introduce IS slot type for scaled-WMMA absorb

For back-to-back scaled WMMAs, the next WMMA's LD_SCALE consumes the
last I slot of the previous WMMA's window — the I cycle is absorbed by
the scale setup and the matrix multiply lands in the V slot that
follows. Previously this was modeled as `avoiding(N, FlavorMasks::All)`
on that slot, which is a tiebreaker in tryCoexecSlot and so doesn't
prevent non-WMMA candidates from being scheduled there.

Replace the lockout with a first-class slot type:

- New `CoExecMask::StageIS = StageI | WMMA = 0xFF` — same I-flavor
capacity as StageI, plus the next scaled WMMA can issue here.
- New `CoExecStageType::IS` for display ("IS").
- New pattern character 'S' parsed in `CoExecInfo::build`, counts toward
ICount so getTypeIndex still reports it as the Nth I slot.
- Each scaled WMMA variant uses an explicit scaled pattern string
(e.g. "0EEIEEISVV") distinct from its unscaled one ("0EEIEEIIVV"),
removing the ternary `HasScaling ? FlavorMasks::All : ...` lockouts.
- The absorb slot's `preferring(N, WMMA)` documents intent — `canCoExec`
now allows WMMA at IS naturally via the mask check, so tryCoexecSlot's
prefer-WMMA wins as a tiebreaker when a WMMA is Available.

Roofline plumbing: switch `DenseMap<uint8_t, unsigned>` to
`SmallDenseMap<uint16_t, unsigned, 16>` because StageIS = 0xFF collides
with `DenseMapInfo<uint8_t>`'s empty-key sentinel. The wider key keeps
0xFF a usable mask value; the SmallDenseMap inline buckets keep the
small map on the stack. A FUTURE comment notes that introducing a
distinct ScaleWMMA flavor would let the roofline differentiate IS slots
from V slots for mixed scaled/unscaled WMMA regions.

Note: this change alone does not improve perf on FA-style kernels. For
back-to-back scaled WMMAs the next WMMA depends on the previous one's
result, so it is always in Pending (never Available) when the IS slot
opens, and tryEffectiveStall picks a no-stall non-WMMA over the
latency-stalled WMMA. A pickNode cycle-advance gated on the IS slot
reaches +12 cycles vs prototype on `mxfp_attn_fwd_kernel` but is held
back from upstream until the underlying chain-ordering issue can be
resolved cleanly. See parking branch
amd/dev/aukerbow/coexec-absorb-scale-wmma-peak.

Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/427cd8271e807a381365658b63bc5068edbc81ac

Git commit 3fa1a08003b44cbea56d45a4946f176602c7b056 by Austin Kerbow on 30/04/2026 at 20:13..
[AMDGPU] SchedModel: account for LD_SCALE absorb in scaled WMMA chains

For back-to-back scaled WMMAs the next WMMA's LD_SCALE consumes the
last I cycle of the previous WMMA's window, so the next WMMA can issue
one cycle earlier than the unscaled-pipeline resource occupancy says.
The IS slot in CoExecInfo already encodes this structurally, but the
sched model was claiming the full N-cycle ReleaseAtCycles, which made
the next WMMA appear in Pending with a non-zero stall at the IS slot.
tryEffectiveStall would then pick a no-stall non-WMMA over the
latency-stalled WMMA and the slot would fill with something that
conflicts with the LD_SCALE in hardware.

Add WriteXDL1PassScaledWMMA and WriteXDL2PassScaledWMMA write classes
with ReleaseAtCycles reduced by 1 (3 and 7 vs the unscaled 4 and 8),
and route WriteWMMAScale_16X16X128_F8F6F4 through them. Latency stays
the same — only the resource hold is shorter, reflecting that the next
scaled WMMA is allowed to begin one cycle earlier.

Result on mxfp_attn_fwd_kernel loop body:
- Before: 1738 warm cycles (+63 vs prototype 1675)
- After: 1692 warm cycles (+17 vs prototype)

The remaining 5-cycle gap to the prior bumpCycle-hack experiment
(1687 warm) is incidental and not yet root-caused; tracked on
amd/dev/aukerbow/coexec-absorb-scale-wmma-peak.

Other scaled WMMA variants (BF16/F16 16x16x32, 16x16x128 fp8/bf8,
32x16x128 f4) still use the unscaled WriteXDL*PassWMMA classes —
applying the same routing to them is a straightforward follow-up.

Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/3fa1a08003b44cbea56d45a4946f176602c7b056

Git commit 713baeb1130962b354dce9cc973ffa19df178f31 by Jeffrey Byrnes on 01/05/2026 at 00:57..
[CoExecSched] Add initial IR corpus + migration targets
https://invent.kde.org/qt/clang/llvm/-/commit/713baeb1130962b354dce9cc973ffa19df178f31

Git commit e00c594cf149693a49efd12f3e13b86871a67cc2 by Jeffrey Byrnes on 01/05/2026 at 18:22..
[AMDGPU] SWAP and PERMLANE*SWAP have RepeatRate 2
https://invent.kde.org/qt/clang/llvm/-/commit/e00c594cf149693a49efd12f3e13b86871a67cc2

Git commit 092c5e7f128a439cd828dbf5f59125740ba79bcc by Jeffrey Byrnes on 01/05/2026 at 18:48..
[AMDGPU] Fix warning from 9b2b47ff56d6
https://invent.kde.org/qt/clang/llvm/-/commit/092c5e7f128a439cd828dbf5f59125740ba79bcc

Git commit cf2b1593fe0c694825d5e347b1caa3bd8d20a27b by Jeffrey Byrnes on 03/05/2026 at 06:06..
[AMDGPU] Add PerfCorpus for static simulator regression testing

Add tooling and baseline data for tracking warm cycle counts from the
AMDGPU static simulator. The perf_test.py script compiles IR test files
with the coexec scheduler and extracts cycle counts from block annotations,
comparing against stored baselines to detect regressions.

Co-Authored-By: Claude Opus 4 <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/cf2b1593fe0c694825d5e347b1caa3bd8d20a27b

Git commit dd58016c009a6b0748752b3542139a3b0cadb1f6 by Jeffrey Byrnes on 03/05/2026 at 17:37..
[AMDGPU] Add migration target to PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/dd58016c009a6b0748752b3542139a3b0cadb1f6

Git commit 02235f9494bf1f29a6154d11a372d2a2e7a882df by Jeffrey Byrnes on 04/05/2026 at 17:26..
[AMDGPU] Use correct values for PerfCoprus/baseline.json
https://invent.kde.org/qt/clang/llvm/-/commit/02235f9494bf1f29a6154d11a372d2a2e7a882df

Git commit d20585a24653d7c83f0c7067d46f3d40cba9a8c9 by Jeffrey Byrnes on 05/05/2026 at 01:45..
[AMDGPU] Default block carried latency to off
https://invent.kde.org/qt/clang/llvm/-/commit/d20585a24653d7c83f0c7067d46f3d40cba9a8c9

Git commit 695f490f856db64d66923294ee49e3f1b04a2a83 by Jeffrey Byrnes on 05/05/2026 at 01:54..
[AMDGPU] Add support for flags in PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/695f490f856db64d66923294ee49e3f1b04a2a83

Git commit 11e15812f48443434b190adbfeb354e48b911f2b by Jeffrey Byrnes on 06/05/2026 at 19:30..
[AMDGPU] Add scheduling only performance evaluation to StaticSim + track sched-mode perf in PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/11e15812f48443434b190adbfeb354e48b911f2b

Git commit 771a4e8f84853df563f6f9bcc557b998461ac9f2 by Jeffrey Byrnes on 06/05/2026 at 22:44..
StaticSim: Classify COPY pseudo-instructions by register class

COPY instructions were falling through to InstClass::OTHER, causing
incorrect co-execution slot accounting (mask=0). This resulted in
significant "Other" WMMACoExec stalls.

Classify COPYs based on register class:
- VGPR↔VGPR or cross-class: VALU (uses I-slots in WMMA windows)
- SGPR↔SGPR: SALU (uses E-slots)

On fp8_FA kernel, this reduces warm cycles from 1660 to 1550 by
properly accounting for COPY slot consumption.

Co-Authored-By: Claude Opus 4 <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/771a4e8f84853df563f6f9bcc557b998461ac9f2

Git commit 1d55ca5740789a62a1735b89d2e2b44e278c3411 by Jeffrey Byrnes on 06/05/2026 at 23:13..
Update sched-only baselines
https://invent.kde.org/qt/clang/llvm/-/commit/1d55ca5740789a62a1735b89d2e2b44e278c3411

Git commit 9cd90edc7c2518e75dd532d071f3a93240894448 by Jeffrey Byrnes on 08/05/2026 at 19:48..
[AMDGPU] Fix some slot preferences / avoids
https://invent.kde.org/qt/clang/llvm/-/commit/9cd90edc7c2518e75dd532d071f3a93240894448

Git commit 8abaa22c8898d33553f9a553f44463e6e08b2645 by Jeffrey Byrnes on 08/05/2026 at 21:57..
Update the perf baselines for previous commit
https://invent.kde.org/qt/clang/llvm/-/commit/8abaa22c8898d33553f9a553f44463e6e08b2645

Git commit 72ebfb9ca711b728d1b382a6ba7dced1aa2f7d7f by Jeffrey Byrnes on 08/05/2026 at 21:58..
[AMDGPU] Teach StaticSim about WMMA + TRANS + VALU multi-shadow hazard

When both WMMA and TRANS instructions are actively executing (their
shadows overlap), a subsequent VALU instruction must stall until the
TRANS shadow clears. This adds detection for this hazard in the static
simulator.

After waiting for the TRANS shadow to clear, we also re-check if the
new cycle lands on a compatible co-execution slot in the WMMA window.

Co-Authored-By: Claude Opus 4 <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/72ebfb9ca711b728d1b382a6ba7dced1aa2f7d7f

Git commit 767b16ecf323c9f3170c39dfb2863f0cd9f78f18 by Jeffrey Byrnes on 08/05/2026 at 22:00..
[AMDGPU] Add hazard for VALU when both WMMA and TRANS are actively executing

WMMA + TRANS + VALU cannot all execute simultaneously. When both a WMMA
and a TRANS instruction are actively executing (their shadows overlap),
a subsequent VALU instruction must stall until at least one of the
shadows clears.

This teaches the scheduler's hazard recognizer about this constraint.

Co-Authored-By: Claude Opus 4 <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/767b16ecf323c9f3170c39dfb2863f0cd9f78f18

Git commit 8316373b4783f093d750f5c591ad7c2bd6a2faf8 by Jeffrey Byrnes on 11/05/2026 at 20:13..
[AMDGPU] Teach tryEffectiveStall about getMissedSlotCosts, and add missed slot cost for DS in slot before I slot

This commit adds notion of cost of scheduling DS instructions in the slot before an I slot. The basic problem is that if we have DS->s_set_vgpr_msb->VALU, the miss the I slot, because the s_set_vgpr_msb can not coissue with the DS instruction. Moreover, we do not have knowledge during pre-ra scheduling as to whether or not we will need an s_set_vgpr_msb instruction. This commit thus takes the design appropach of pre-ra scheduling being pessimistic (perhaps overly so) about RA for the purpose of avoding breaking coexec windows. This design relies on later passes to clean up cases where PreRA scheduling was overly pessimistic.

This commit also introduces the rudiments of more balanced reasoning about instantenous stall costs. Currently the CoExec scheduler gives high priority for stall avoidance, but this avoidance misses a part of the equation. If we stall now we may avoid a slot miss in the future -- in the case of this commit, if we stall for VALU in the E slot, then we can be sure to hit the I slot -- as opposed to avoiding the stall and scheduling DS and (potentially) missing the I slot. In general, there are cases where stalling now means less missed slots. Or, again this case, stalling now means we miss an E slot, but we avoid missing an I slot (which hints at the notion of I slots being more "valuable" than E slots).

There are multiple interesting extentions to this:
1. stalling in a window vs missing a future slot -- this implies that the exact slot we miss is different, and it is not equally important to hit each slot. So, we may benefit from teaching the scheduler about the cost of missing each type of slot (based on roofline coexec in unsched region and/or how exlusive the missed slot is).
2. The design is such that we pessimistically assume s_set_vgpr_msb will be necessary between ds_load + VALU -- preRA is overly pessimistic as to minimize broken windows , with the assumption that later passes can fix up any overly pessimistic choices. But, the implementatino allows for exploring other design choices, such as a probablistic model which gives fractional costs to missed VALU slot due to s_set_vgpr_msb based on observed frequencies.
3. Other uses cases - placing WMMA in s-slot: missed slots from scheduling it now vs missed slots produced by deferring it.
https://invent.kde.org/qt/clang/llvm/-/commit/8316373b4783f093d750f5c591ad7c2bd6a2faf8

Git commit 48738b171be3dd49af7131aa12bd9c7c2faf5bc9 by GitHub (on behalf of Cherniavskii, Ilia) on 12/05/2026 at 18:56..
[AMDGPU] Add live interval register pressure-aware rescheduling stage (#6028)

Machine scheduler's register pressure (RP) heuristic computes instant RP
based on live interval segments at a given moment, which is an
optimistic estimate of the number of registers needed. This quantity can
sometimes be misleading, resulting in unnecessary splits or spills in
RA.

To address this, we introduce a live interval register pressure-aware
scheduling stage that estimates RP based on live interval interference.
If a significant difference between instant pressure and live
interval-based pressure is detected, we reschedule the region with a
lower VGPR limit.

Test:
llvm-lit -v llvm/test/CodeGen/AMDGPU/lirp-reschedule.mir
perf testing on a corpus of kernels (llvm/lib/Target/AMDGPU/PerfCorpus)

Co-authored-by: Ilya Chernyavsky <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/48738b171be3dd49af7131aa12bd9c7c2faf5bc9

Git commit 07b53b55eb44db7a0a92ca736d86532703fcd2da by Jeffrey Byrnes on 12/05/2026 at 23:41..
[AMDGPU] Treat COPYs as instructions for scheduling
https://invent.kde.org/qt/clang/llvm/-/commit/07b53b55eb44db7a0a92ca736d86532703fcd2da

Git commit b85ad4a0a3b35a3f810fc9389c448ba477e44fb6 by Jeffrey Byrnes on 13/05/2026 at 17:23..
[AMDGPU] Add some documentation for compute roofline coexec
https://invent.kde.org/qt/clang/llvm/-/commit/b85ad4a0a3b35a3f810fc9389c448ba477e44fb6

Git commit e2ad50f86bcb37a09596e5f53b22e72b2e6fdf3a by Jeffrey Byrnes on 13/05/2026 at 19:02..
[AMDGPU] Prioritize CoexecWindows by ready instructions
https://invent.kde.org/qt/clang/llvm/-/commit/e2ad50f86bcb37a09596e5f53b22e72b2e6fdf3a

Git commit e1beeeb20543c5cbae8b3d2f4a91790414bc92b5 by Jeffrey Byrnes on 13/05/2026 at 19:02..
WindowSlotDemand is based on CoexecInfo for nextTargetSU, and TRANS + MultiVALU have WindowSlotDemand
https://invent.kde.org/qt/clang/llvm/-/commit/e1beeeb20543c5cbae8b3d2f4a91790414bc92b5

Git commit fd61d8b718e55468f13af1b15acf9bb605e7044c by Jeffrey Byrnes on 13/05/2026 at 19:08..
[AMDGPU] Extend tryShadowMix to reason in Consumer vs Consumer case, and take into account CoexecWindow
https://invent.kde.org/qt/clang/llvm/-/commit/fd61d8b718e55468f13af1b15acf9bb605e7044c

Git commit 0d6f2eaa61c54b5c1eb1a261af30ba07c4a41544 by Jeffrey Byrnes on 13/05/2026 at 22:31..
[AMDGPU] Clamp the RegionDemand by the instruction supply in the region
https://invent.kde.org/qt/clang/llvm/-/commit/0d6f2eaa61c54b5c1eb1a261af30ba07c4a41544

Git commit d2140d5790abd13879def876eb2d6b6738ebde79 by Austin Kerbow on 15/05/2026 at 23:57..
[AMDGPU] Allow LLC_PATH env override in PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/d2140d5790abd13879def876eb2d6b6738ebde79

Git commit ab229e89b3e2e6b7c946a20aaa7bec4caab4cf7b by Austin Kerbow on 19/05/2026 at 06:37..
[AMDGPU] CoExec roofline: add TRANS shadow producer (excess-capacity)

Each TRANS executes in 2 cycles; its 2nd cycle is a co-exec shadow that
accepts core/side MACC + off-pipe ops (per SPG §5.3.5.2.2). Previously
TRANS appeared only as a consumer in computeRooflineCoExec, so its
shadow capacity was not counted in Roofline.TotalSlots and downstream
heuristics that read RemainingExposed.

Use an excess-capacity model: count one StageTR slot per TRANS that
does not fit into a WMMA I/IS slot. TRANS that lands in a WMMA window
already gets its 2-cycle execution absorbed by the window pattern, so
adding a separate shadow there would double-count. The mask StageTR
(All & ~TRANS) matches what CoExecInfo templates already use for 'T'
slots, so semantics stay consistent across the supply side.
https://invent.kde.org/qt/clang/llvm/-/commit/ab229e89b3e2e6b7c946a20aaa7bec4caab4cf7b

Git commit de497195237640047e67b7eb78517d6e54eea6d5 by Austin Kerbow on 19/05/2026 at 06:37..
[AMDGPU] CoExec roofline: model multi-cycle VALU as a producer

Multi-cycle VALU (CVT, PERM, etc with RepeatRate > 1) cannot issue
within a WMMA window — it has its own coexec window. Per the rules:

Issue cycle: consumed by the multi-cycle VALU itself
Shadow cycles (RR-1): math SIMD blocked, but SALU/MEM/CTRL can
co-issue (StageE-like)

Treat MultiCycleVALU like WMMA in computeRooflineCoExec: skip it as a
consumer, and add (RepeatRate - 1) StageE slots to the SlotTypes map
(its shadow). The issue cycle is self-filled by the producer.

Per-window demand for MCV is already wired up in Jeff's framework via
WindowSlotDemand::fromCoExecInfo + getCoExecInfo's MCV branch (uniform
RR-1 'E' pattern), so this only adds the supply-side accounting needed
for the roofline / RemainingExposed-driven heuristics to see MCV's
shadow capacity. Pairs with the TRANS shadow producer added earlier.
https://invent.kde.org/qt/clang/llvm/-/commit/de497195237640047e67b7eb78517d6e54eea6d5

Git commit 8c7b666a8de845493d36cce5d139e0c56f990eab by Austin Kerbow on 19/05/2026 at 06:37..
[AMDGPU] PerfCorpus: regenerate baselines
https://invent.kde.org/qt/clang/llvm/-/commit/8c7b666a8de845493d36cce5d139e0c56f990eab

Git commit 70fd785ad668eb0643985dc2283f0a16a62a5783 by Jeffrey Byrnes on 19/05/2026 at 19:34..
[AMDGPU] Prioritize remaining cycles for tryCriticalResourceDep

The way we sort HWUi for tryCriticalResource and tryCriticalResourceDependency may need some work.

Conceptually, tryCriticalResource is supposed to keep the critical resource busy, and tryCriticalResourceDependency is supposed to ensure we have instructions ready to keep the criticalResource maximally busy.

For the former, this generally means scheduling SUs that execute on HWUI with exposed cycles -- because if such an instruction has reached this heuristic, that means the HWUI is available with minimal stalls.

But, for the latter, we must prioritize instructions with HWUIs that have lots of usage, even if there are no exposed cycles. For example, if we have say 100 lds instructions and we expect all of the latency to be hidden behind wmma, it is still a priority to make these ready, otherwise we may end up in a situation where we have failed to make the lds instructions ready and they are not coexecuted under the wmma.

This changes the HWUI priority of tryCriticalResourceDependency such that we give highest priority to HWUIs with the greatest number of remaining + non-ready cycles.
https://invent.kde.org/qt/clang/llvm/-/commit/70fd785ad668eb0643985dc2283f0a16a62a5783

Git commit ef352e17f7e2802a2c840022707e506db8be726c by Jeffrey Byrnes (on behalf of hidekisaito) on 19/05/2026 at 21:59..
[AMDGPU] SIFoldOperands: constant-fold S_ADD/S_SUB with immediate operands (#198410)

Extend SIFoldOperands::tryConstantFoldOp to recognise three patterns
* ADD/SUB(imm, imm) -> S_MOV_B32 (LHS +/- RHS)
* ADD x, 0 -> COPY x (Also `0 + x`)
* SUB x, 0 -> COPY x (SUB is not commutable)

Assisted-by: Claude Opus 4.7
(cherry picked from commit 5ff6c5e4a0f7882c2b9b52dff6710ff33c11a74c)
https://invent.kde.org/qt/clang/llvm/-/commit/ef352e17f7e2802a2c840022707e506db8be726c

Git commit 1e7aaa28433f0126992bc8b65e3776dc340deee7 by Jeffrey Byrnes on 19/05/2026 at 22:23..
[AMDGPU] Do not require ld_scale read cycle to be greater than IssueCycle

IssueCycle depends on XDL functional unit stall, so it will always be the first V slot in WMMA windows. By requiring ld_scale read to always be at least the IssueCycle, we do not allow it to fall in previous I slot
https://invent.kde.org/qt/clang/llvm/-/commit/1e7aaa28433f0126992bc8b65e3776dc340deee7

Git commit eed55d7ed1ceb46eb662d7f1e7755be02fffdc44 by Jeffrey Byrnes on 19/05/2026 at 22:27..
Fix naming
https://invent.kde.org/qt/clang/llvm/-/commit/eed55d7ed1ceb46eb662d7f1e7755be02fffdc44

Git commit 8a4104ec75db45e7d4eeb61efe20f853209a392d by GitHub (on behalf of Byrnes, Jeffrey) on 19/05/2026 at 22:37..
[AMDGPU] Do not require ld_scale read cycle to be greater than IssueCycle (#6229)
https://invent.kde.org/qt/clang/llvm/-/commit/8a4104ec75db45e7d4eeb61efe20f853209a392d

Git commit 0f085eaf823e5c824df4646c6d00c1abbcc11d56 by Jeffrey Byrnes on 19/05/2026 at 22:42..
[AMDGPU] Don't insert delay_alu for 1 waves-per-eu
https://invent.kde.org/qt/clang/llvm/-/commit/0f085eaf823e5c824df4646c6d00c1abbcc11d56

Git commit db7a813e110116d22431b207a323bb7ebc75f80a by Jeffrey Byrnes on 19/05/2026 at 22:46..
[AMDGPU] Add vgpr-threshold flag back to gluon/fp8_GEMM
https://invent.kde.org/qt/clang/llvm/-/commit/db7a813e110116d22431b207a323bb7ebc75f80a

Git commit ed697a5d2cc57c7f244bd611e4384e8ba9b2deae by Austin Kerbow on 21/05/2026 at 19:18..
[AMDGPU] Include v16f32 accumulators in IsC_F32 for WMMA profiles

Not all WMMA with 32bit accumulators were included in va_vdst
optimizations.
https://invent.kde.org/qt/clang/llvm/-/commit/ed697a5d2cc57c7f244bd611e4384e8ba9b2deae

Git commit d7237dc30c35e140a02df404837c2e73c363dab9 by Austin Kerbow on 21/05/2026 at 20:55..
[AMDGPU] Bound the ShadowMix IsReachable scan in CoExec scheduler

tryShadowMix iterated every pending SU of the needed flavor and ran two
IsReachable DFS probes per match. On large DAGs this scaled as O(N^2)
DFS per pickNode comparison and dominated compile time.

Cap the inner loop with ShadowMixIsReachableBudget (default 16) and
move ShadowMixLookaheadDepth alongside it next to tryShadowMix. Also
skip the loop entirely when both candidates are producer-class, since
wouldHelpEnable short-circuits to false on both sides and no iteration
can change the outcome.
https://invent.kde.org/qt/clang/llvm/-/commit/d7237dc30c35e140a02df404837c2e73c363dab9

Git commit 2e06b08458f8865a3ed1fcf5c4d1dbb9dd5d4bd0 by Austin Kerbow on 21/05/2026 at 21:44..
Merge main into CoExecScheduler

Update to Triton llvm-hash: 7ec6f177111478c0436f773ba9d836b4afaac2c6
https://invent.kde.org/qt/clang/llvm/-/commit/2e06b08458f8865a3ed1fcf5c4d1dbb9dd5d4bd0

Git commit 0df6a16f5654a7748e97367f302993ca97884777 by Jeffrey Byrnes on 27/05/2026 at 23:27..
[AMDGPU] Add fence-only mode for block carried latency
https://invent.kde.org/qt/clang/llvm/-/commit/0df6a16f5654a7748e97367f302993ca97884777

Git commit 5a74b15d1e2eab1739b48a3eb133a0780197e414 by Jeffrey Byrnes on 28/05/2026 at 00:39..
[AMDGPU] Do not add latency for async->async
https://invent.kde.org/qt/clang/llvm/-/commit/5a74b15d1e2eab1739b48a3eb133a0780197e414

Git commit 46c9c8a546a135a79935881ff5cb3405ca45aaa9 by Jeffrey Byrnes on 01/06/2026 at 18:24..
[AMDGPU] Fix bug in computeSlotsMissed
https://invent.kde.org/qt/clang/llvm/-/commit/46c9c8a546a135a79935881ff5cb3405ca45aaa9

Git commit bc2c8d2a3edb95be40449af2c4e3174652859b8f by Jeffrey Byrnes on 02/06/2026 at 19:32..
[AMDGPU] Move false / latency handling into adjustSchedDep
https://invent.kde.org/qt/clang/llvm/-/commit/bc2c8d2a3edb95be40449af2c4e3174652859b8f

Git commit ca98c3fb591b3caad79ae50d1fcc9095a3d4e986 by Hideki Saito on 03/06/2026 at 20:46..
[AMDGPU] Compare two DSReads and try to decide which should be scheduled earlier

If the schedule region is a whole loop body, and if there are DSReads feeding to
the next iteration, try to influence the schedule by the consumption order of
the next iteration, in trying to avoid last of DSReads consumed first.
Tracks at sub-vreg level.

Assisted-by: Opus 4.7 Extra High
https://invent.kde.org/qt/clang/llvm/-/commit/ca98c3fb591b3caad79ae50d1fcc9095a3d4e986

Git commit 4d1af17cf8d8e773bf7b1cc093be1c3ded55b8ac by GitHub (on behalf of Ido, Hideki Saito) on 03/06/2026 at 20:52..
[AMDGPU] Compare two DSReads and try to decide which should be scheduled earlier (#6360)

Assisted-by: Opus 4.7 Extra High
https://invent.kde.org/qt/clang/llvm/-/commit/4d1af17cf8d8e773bf7b1cc093be1c3ded55b8ac

Git commit b968caaeb5d5985a39bb668c826523066cda31ff by GitHub (on behalf of Cahoon, Brendon) on 04/06/2026 at 16:49..
[InstCombine] Fold identity shufflevectors across control flow (#6435)

Eliminate redundant shufflevector chains that occur across Phis when the
inputs use the same masks.
https://invent.kde.org/qt/clang/llvm/-/commit/b968caaeb5d5985a39bb668c826523066cda31ff

Git commit 14524a62762eb5bb5d1d2e0742cbf1202f3e4d17 by Jeffrey Byrnes on 04/06/2026 at 17:25..
[AMDGPU] Do not combine ds_loads for single block loops if the combine would create dep on all WMMA
https://invent.kde.org/qt/clang/llvm/-/commit/14524a62762eb5bb5d1d2e0742cbf1202f3e4d17

Git commit cc20ee2e112b3338c9c791d77e9ddb3dab0e1df6 by Austin Kerbow (on behalf of Jay Foad) on 04/06/2026 at 17:59..
[AMDGPU] Inline SIInsertWaitcnts::getExpertSchedulingEventType. NFC.
https://invent.kde.org/qt/clang/llvm/-/commit/cc20ee2e112b3338c9c791d77e9ddb3dab0e1df6

Git commit 571563c249a75299ca279a152784293eea4af4b6 by Austin Kerbow (on behalf of Jay Foad) on 04/06/2026 at 17:59..
[AMDGPU] Handle WAR hazards
https://invent.kde.org/qt/clang/llvm/-/commit/571563c249a75299ca279a152784293eea4af4b6

Git commit 159b0b6a4b4aeb68d2ff3dfdc5a36c6cf5b9a49f by Austin Kerbow on 04/06/2026 at 18:10..
Revert "[AMDGPU] Handle WAR hazards"

This reverts commit 571563c249a75299ca279a152784293eea4af4b6.
https://invent.kde.org/qt/clang/llvm/-/commit/159b0b6a4b4aeb68d2ff3dfdc5a36c6cf5b9a49f

Git commit 719b4ec2d560536ab8db01bbc391baeda57238f1 by Austin Kerbow on 04/06/2026 at 18:14..
Enable expert scheduling and anti-hints in PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/719b4ec2d560536ab8db01bbc391baeda57238f1

Git commit 0f478d6fb230113feff66895b88f8698320f2657 by Jeffrey Byrnes on 04/06/2026 at 20:40..
[AMDGPU] WIP: Add sliding window shufflevector opt to cleanup weird shufflevectors
https://invent.kde.org/qt/clang/llvm/-/commit/0f478d6fb230113feff66895b88f8698320f2657

Git commit f067d9aa134f26ff01ba428ed17fdeceb6507a77 by Jeffrey Byrnes on 04/06/2026 at 22:37..
[AMDGPU] using divergent/uniform information in ISel of zext
https://invent.kde.org/qt/clang/llvm/-/commit/f067d9aa134f26ff01ba428ed17fdeceb6507a77

Git commit ebd589b1d6a909c0704c73429096941af0ba8a17 by Jeffrey Byrnes on 04/06/2026 at 22:40..
[AMDGPU] Add ISel patterns for uniform usubsat
https://invent.kde.org/qt/clang/llvm/-/commit/ebd589b1d6a909c0704c73429096941af0ba8a17

Git commit 208081a31fadf030826f1989dc3391c88e53947e by Jeffrey Byrnes on 04/06/2026 at 23:37..
[AMDGPU] LIRP clamps VGPR limits per region
https://invent.kde.org/qt/clang/llvm/-/commit/208081a31fadf030826f1989dc3391c88e53947e

Git commit 50cdaeed3b84421e468b1cac32de2da97feab785 by Jeffrey Byrnes on 04/06/2026 at 23:47..
[AMDGPU] Use more reasonable latencies for barrier edges
https://invent.kde.org/qt/clang/llvm/-/commit/50cdaeed3b84421e468b1cac32de2da97feab785

Git commit c90b49840af3321561747bef864689b6805c348d by Jeffrey Byrnes on 04/06/2026 at 23:53..
[AMDGPU] Downcast min_i64 during selection
https://invent.kde.org/qt/clang/llvm/-/commit/c90b49840af3321561747bef864689b6805c348d

Git commit 8be8d08b882d3f321d281c3e8755f5c9ee4e7749 by Jeffrey Byrnes on 04/06/2026 at 23:56..
[AMDGPU] Add latency to pad between valu->memory instructions
https://invent.kde.org/qt/clang/llvm/-/commit/8be8d08b882d3f321d281c3e8755f5c9ee4e7749

Git commit 5d451570fc4efba78abbfa46c4ec5821b05442a3 by Jeffrey Byrnes on 05/06/2026 at 00:03..
Update PerfCorpus for bulk change
https://invent.kde.org/qt/clang/llvm/-/commit/5d451570fc4efba78abbfa46c4ec5821b05442a3

Git commit 77b3a9596835ca58059e0a507b05bad5c47f1700 by Jeffrey Byrnes on 05/06/2026 at 00:13..
[AMDGPU] Refresh PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/77b3a9596835ca58059e0a507b05bad5c47f1700

Git commit 0ea4801d495ebf854be8c36546722e7115d60ce2 by Austin Kerbow on 08/06/2026 at 16:02..
Merge main into CoExecScheduler

Update to Triton llvm-hash: 62b7cf9623fc310525f39ed69aaecc318a909731
https://invent.kde.org/qt/clang/llvm/-/commit/0ea4801d495ebf854be8c36546722e7115d60ce2

Git commit 7785d9a28edf4b3d9929d3bf46d1fe82d12a824c by Jeffrey Byrnes on 08/06/2026 at 19:44..
Remove fp4 flag from PerfCorpus
https://invent.kde.org/qt/clang/llvm/-/commit/7785d9a28edf4b3d9929d3bf46d1fe82d12a824c

Git commit 83cfe02a01a36b7c2a320648cb1c9e695f8f3815 by Austin Kerbow on 08/06/2026 at 20:29..
Merge merge-triton-llvm-bump-62b7cf96 into CoExecScheduler-staging
https://invent.kde.org/qt/clang/llvm/-/commit/83cfe02a01a36b7c2a320648cb1c9e695f8f3815

Git commit 24a4e2788669a873a6d10a4d87943f29182453d8 by GitHub (on behalf of Sachkov, Alexey) on 10/06/2026 at 09:28..
[NFC] Widen CoExec mask (#6478)

Motivation is to support more co-exec slot flavors present in MI350.

Also replaced the raw type with an alias which should simplify further
changes (or merge with the `InstructionFlavor` if we decide to do so).
https://invent.kde.org/qt/clang/llvm/-/commit/24a4e2788669a873a6d10a4d87943f29182453d8

Git commit a9e7d94e35f759106a87fb84dcf50c3b567a2c0d by Jeffrey Byrnes on 10/06/2026 at 18:55..
[AMDGPU] Add anti-hint to avoid xcnt
https://invent.kde.org/qt/clang/llvm/-/commit/a9e7d94e35f759106a87fb84dcf50c3b567a2c0d

Git commit c931baef9e592740b599d3f31f8a0f39e85ec4bf by Austin Kerbow (on behalf of Alexander Weinrauch) on 11/06/2026 at 18:56..
[AMDGPU] Track LDS DMA VGPR source reads in expert scheduling

Cherry-pick of llvm/llvm-project#203292.

LDS DMA instructions are marked as VALU but we need to treat them as
FLAT/vmem instructions for expert mode waitcnt insertion. This means:
- getEventsFor: emit the vm_vsrc WAR wait for writes to the DMA's input
VGPRs.
- generateWaitcntInstBefore: do not relax the va_vdst wait before an
LDS DMA, so RAW hazards on its input VGPRs are protected.

Test CHECK lines regenerated against CoExecScheduler-staging; output is
identical to upstream.
https://invent.kde.org/qt/clang/llvm/-/commit/c931baef9e592740b599d3f31f8a0f39e85ec4bf

Git commit 397d7a8f1995589ab6ab6f52cf47033acefc0d8b by Jeffrey Byrnes on 11/06/2026 at 19:45..
[AMDGPU] Accurately model CoExec slots for 32x16x128_f4 wmma
https://invent.kde.org/qt/clang/llvm/-/commit/397d7a8f1995589ab6ab6f52cf47033acefc0d8b

Git commit fff190ab96bce94ab7b5b0f6def60d1f1b2e1299 by Jeffrey Byrnes on 11/06/2026 at 20:31..
[AMDGPU] Add threshold for rounding up for demanded slots

The previos commit -- 397d7a8f1995589ab -- causes a large regression to the fp4 gemm kernel in PerfCorpus. This is because we now have more ISlots per WMMA (the correct number of ISlots). In this kernel, we have 10 or so VALU compared to 64 WMMA. Since we round up when calculating the demanded I slots, we end up trying to have 1 VALU available per WMMA. This is leading to the scheduler aggressively trying to enable the few VALU, and is leading to suboptimal scheduling.

Previously, we always rounded up. This is good for cases where our modulo is close the number of WMMA, but causes regressions when the modulo is close to 0. This commit adds a percentage threshold for rounding up.
https://invent.kde.org/qt/clang/llvm/-/commit/fff190ab96bce94ab7b5b0f6def60d1f1b2e1299

Git commit 295d3825c9e788ef671ae4aba00690c02cde71ea by Jeffrey Byrnes on 12/06/2026 at 20:16..
[AMDGPU] More precise scheduler modelling of OOO pessimism for wait vdst
https://invent.kde.org/qt/clang/llvm/-/commit/295d3825c9e788ef671ae4aba00690c02cde71ea

Git commit ecfeb4747c35401e55dfd66a0d2562f72bfdd28f by Jeffrey Byrnes on 12/06/2026 at 20:22..
[AMDGPU] Use accurate total window size for 32x16x128_f4

We continue to see significant fluctuations in this fp4 kernel with changes to the scheduler. There are some issues with the kernel, but maybe this fragility is pointing to the scheduler missing something in the heuristics
https://invent.kde.org/qt/clang/llvm/-/commit/ecfeb4747c35401e55dfd66a0d2562f72bfdd28f

Git commit 32f7051ba18586533f139bf3bb725cbca63279af by Jeffrey Byrnes on 15/06/2026 at 22:12..
[AMDGPU] Refine i8 extractelement cost model
https://invent.kde.org/qt/clang/llvm/-/commit/32f7051ba18586533f139bf3bb725cbca63279af

Git commit 20ea3e96a8ded1636ef024559e546b2602ca2e26 by Jeffrey Byrnes on 15/06/2026 at 23:32..
[AMDGPU] Fix bug with CarriedLatencyMode + Migrate 64 bit downcasting into Subtarget feature
https://invent.kde.org/qt/clang/llvm/-/commit/20ea3e96a8ded1636ef024559e546b2602ca2e26

Git commit d2e882fb314d391a62d984a60d241813573f8da1 by Jeffrey Byrnes on 16/06/2026 at 20:58..
[AMDGPU] Set a more reasonable default for LiveIntervalRPVGPRReductionEpilogue
https://invent.kde.org/qt/clang/llvm/-/commit/d2e882fb314d391a62d984a60d241813573f8da1

Git commit ee2276cd74994f2c6432eb7942e538ef5286ab4a by Jeffrey Byrnes on 16/06/2026 at 21:05..
Refresh perf corpus for some kernels
https://invent.kde.org/qt/clang/llvm/-/commit/ee2276cd74994f2c6432eb7942e538ef5286ab4a

Git commit 838ea2e6fd4402b3c2558290908c2cd42fa80792 by Volkan Keles on 17/06/2026 at 15:42..
[AMDGPU] CoExecSched: Skip boundary nodes when scanning WMMA successors

When a WMMA instruction is live-out of a fall-through region, its
successor dependency edge points at the boundary ExitSU, which has no
MachineInstr. CandidateHeuristics::initialize() walked these successors
and passed the null MI straight into classifyFlavor(), crashing on the
dereference. Skip successors with no MachineInstr before classifying them.
https://invent.kde.org/qt/clang/llvm/-/commit/838ea2e6fd4402b3c2558290908c2cd42fa80792

Git commit 7cfb30d60c06efefdc6c29407fafa4a984198a87 by Jeffrey Byrnes on 17/06/2026 at 16:32..
Revert "[AMDGPU] WIP: Add sliding window shufflevector opt to cleanup weird shufflevectors"

This reverts commit 0f478d6fb230113feff66895b88f8698320f2657.

Superceded by 32f7051ba185 -- underlying issue fixed
https://invent.kde.org/qt/clang/llvm/-/commit/7cfb30d60c06efefdc6c29407fafa4a984198a87

Git commit a99770587dbfb274b13507f6d2f32f2b01465c10 by Hideki Saito on 18/06/2026 at 22:53..
Align COPY's classifyFlavor with getCoExecMaskForCopy
https://invent.kde.org/qt/clang/llvm/-/commit/a99770587dbfb274b13507f6d2f32f2b01465c10

Git commit 2e36df49714843e6c1904b12d9eb2814eaf93726 by GitHub (on behalf of Ido, Hideki Saito) on 18/06/2026 at 22:58..
Align COPY's classifyFlavor with getCoExecMaskForCopy (#6633)

COPY was classified as Other and that was a mismatch from CoExecMask expectation for COPY. Now aligned.
https://invent.kde.org/qt/clang/llvm/-/commit/2e36df49714843e6c1904b12d9eb2814eaf93726

Git commit 109878eaf4ec7e4e8e7e0bb30d42e78dd661bb2d by Jeffrey Byrnes on 19/06/2026 at 16:32..
Refresh MOE perf corpus
https://invent.kde.org/qt/clang/llvm/-/commit/109878eaf4ec7e4e8e7e0bb30d42e78dd661bb2d

Git commit f6d7ba60699366146cf68ba250da27134b536284 by Jeffrey Byrnes on 19/06/2026 at 22:52..
[AMDGPU] Precommit test to show impact of waitcnt fix
https://invent.kde.org/qt/clang/llvm/-/commit/f6d7ba60699366146cf68ba250da27134b536284

Git commit ce11c4c58903761554784b5d314f7361d30faadf by Jeffrey Byrnes on 22/06/2026 at 19:36..
Document TryCoexecSlot
https://invent.kde.org/qt/clang/llvm/-/commit/ce11c4c58903761554784b5d314f7361d30faadf

Git commit 194698d4d0e33d3bb0b286ece91a75ea2700aaf7 by Jeffrey Byrnes on 23/06/2026 at 00:41..
Document tryMemoryPipeline
https://invent.kde.org/qt/clang/llvm/-/commit/194698d4d0e33d3bb0b286ece91a75ea2700aaf7

Git commit a826e510fc75135a9b99d99de500bc95c0f7e8be by Jeffrey Byrnes on 23/06/2026 at 02:55..
Document tryCriticalResource
https://invent.kde.org/qt/clang/llvm/-/commit/a826e510fc75135a9b99d99de500bc95c0f7e8be

Git commit 24852a1575c7c60ce26497c68fc9f9b97ff46ba5 by Jeffrey Byrnes on 24/06/2026 at 19:47..
Document tryCriticalResourceDependency
https://invent.kde.org/qt/clang/llvm/-/commit/24852a1575c7c60ce26497c68fc9f9b97ff46ba5

Git commit ad81e32b4b46695419e5f341cdd8d3df719ce502 by Jeffrey Byrnes on 01/07/2026 at 14:21..
[AMDGPU] Fix amdgpu-waitcnt-forcezero for gfx1250 + include DMA ops
https://invent.kde.org/qt/clang/llvm/-/commit/ad81e32b4b46695419e5f341cdd8d3df719ce502

Git commit e4ea19cc532bf048338df4fb2d33884e45d65c5b by Jeffrey Byrnes on 01/07/2026 at 14:34..
[AMDGPU] Add control to force emit v_nops
https://invent.kde.org/qt/clang/llvm/-/commit/e4ea19cc532bf048338df4fb2d33884e45d65c5b

Git commit 1a7e984d818e5074b8327860974758438ae76252 by Austin Kerbow (on behalf of Kerbow, Austin) on 01/07/2026 at 19:34..
Merge triton-lang/triton-main-20260626 into CoExecScheduler (#6812)

Update to Triton llvm-hash: 850a2b1b975c061ae0fc982ba68064d305485cb2

llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SISchedule.td
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
https://invent.kde.org/qt/clang/llvm/-/commit/1a7e984d818e5074b8327860974758438ae76252

Git commit 7d8bba5386acd387f4b7ec9495886cc02298f3d7 by Jeffrey Byrnes on 06/07/2026 at 15:58..
Update PerfCorpus from merge
https://invent.kde.org/qt/clang/llvm/-/commit/7d8bba5386acd387f4b7ec9495886cc02298f3d7

Git commit c9f374c454c1536390b116cd7945b4854d57b9bd by Jeffrey Byrnes on 06/07/2026 at 18:58..
Move RepeatRate to searchable tables
https://invent.kde.org/qt/clang/llvm/-/commit/c9f374c454c1536390b116cd7945b4854d57b9bd

Git commit 5ef7c068a8b494d76c0c80c9b73cc5848468de18 by GitHub (on behalf of Sachkov, Alexey) on 08/07/2026 at 15:19..
Fix conversion between CoExecMaskT and InstructionFlavor (#6832)

`flavorBit` returns an "index" of a flavor in the enum which does not
match `CoExecMask`s definition, making us incorrectly think that an
instruction can be put into a slot.
https://invent.kde.org/qt/clang/llvm/-/commit/5ef7c068a8b494d76c0c80c9b73cc5848468de18

Git commit 56421f921b1dc05335fa8a6cfa4aeddd0ceb80c7 by Alexander Weinrauch on 08/07/2026 at 16:32..
Add missing waitcnts between local_write and tdm store
https://invent.kde.org/qt/clang/llvm/-/commit/56421f921b1dc05335fa8a6cfa4aeddd0ceb80c7

Git commit db4972674de235fc71a3ae0c8da60d0f219bfacd by jerryyin on 15/07/2026 at 14:29..
[AMDGPU][MachineLICM] Hoist loop-invariant readfirstlane out of uniform loops

readfirstlane is convergent, so MachineLICM never hoists it. But a
v_readfirstlane_b32 whose operands (including its implicit EXEC use) are
loop-invariant is safe to hoist: in a uniform loop the first active lane is
the same every iteration, so the broadcast is loop-invariant.

- Add TargetInstrInfo::isConvergentInstrHoistable() (default false) and let
MachineLICM consult it instead of bailing unconditionally on convergent.
- SIInstrInfo opts in V_READFIRSTLANE_B32 (guarded by
-amdgpu-hoist-uniform-readfirstlane).
- SIRegisterInfo::shouldAnalyzePhysregInMachineLoopInfo tracks EXEC so the
loop-invariance check gates hoisting to uniform loops (EXEC not redefined);
divergent loops keep the broadcast, preserving correctness.
https://invent.kde.org/qt/clang/llvm/-/commit/db4972674de235fc71a3ae0c8da60d0f219bfacd