[qt/clang/llvm-project]: Summary of bulk changes made

Git repository change summary for qt/clang/llvm-project
Pushed by mirror-service into branch 'upstream/users/petar-avramovic/vcc-bool-in-reg-fix'.
Changed from 0000000000000000000000000000000000000000 to 126447232820c207b88f4687fab34a68c0b03445
Acknowledgement was received that this change introduces only existing code that has been pushed to another public open source repository.

This change contains the following new commits:

Git commit 840060f2f85c2d3f8ebe1c9304770d682e4141f6 by GitHub (on behalf of Pengcheng Wang) on 28/07/2026 at 11:19..
[RISCV] Don't move memory instructions across calls in isSafeToMove (#212236)

RISCVInstrInfo::isSafeToMove scans the instructions between From and To
to decide whether a memory instruction can be moved, but it only treated
mayStore() instructions as barriers. Calls on RISC-V are modeled with
isCall() and a register mask rather than mayStore(), so a load could be
moved across a call even though the callee may clobber the loaded
memory.

RISCVVectorPeephole::foldVMergeToMask uses this helper via ensureDominates()
to sink a load into a masked load when folding it into a vmerge, which
produced wrong code when the load was sunk past a call.

Instead of hand-rolling the barrier check, call MachineInstr::isSafeToMove
on each intervening instruction to populate SawStore. That is the same
helper used on From below, and it already treats calls (as well as PHIs
and ordered memory references) as stores.

This fixes #212226.

Assisted-by: TRAE CLI (DeepSeek V4 Pro)
https://invent.kde.org/qt/clang/llvm-project/-/commit/840060f2f85c2d3f8ebe1c9304770d682e4141f6

Git commit ff46298372dc64d8fb56f1397c2914772b815605 by GitHub (on behalf of Arseniy Obolenskiy) on 28/07/2026 at 11:25..
[mlir][SPIR-V] Support bitwise and/or/xor in gpu reduction lowering (#202351)
https://invent.kde.org/qt/clang/llvm-project/-/commit/ff46298372dc64d8fb56f1397c2914772b815605

Git commit bcdff65a953758e3a72cf99586c6ce809d4aaf9e by GitHub (on behalf of Nikolas Klauser) on 28/07/2026 at 11:33..
[libc++] Simplify some meta-programming in tuple (#212436)

This does two things:
- replace `_Not<T>::value` with `!T::value` when we already evaluate
lazily
- remove `_And`s that aren't useful because they only have a single
argument
https://invent.kde.org/qt/clang/llvm-project/-/commit/bcdff65a953758e3a72cf99586c6ce809d4aaf9e

Git commit 321642826552ff4e4c7d67ea236f8669d4598c9f by GitHub (on behalf of A. Jiang) on 28/07/2026 at 11:35..
[libc++][test] Disable test coverage for `_BitInt` for non-libc++ implementations (#212435)

Currently, library support for `_BitInt(N)` is an extension explicitly
supported by libc++. However, when using Clang with other standard
library implementations, `TEST_HAS_BITINT` is currently `1` as the
condition only detects compiler support of `_BitInt`.

This patch disables `_BitInt` coverage for other implementations for
now.
https://invent.kde.org/qt/clang/llvm-project/-/commit/321642826552ff4e4c7d67ea236f8669d4598c9f

Git commit abd3b3a1445b5a8eeffae5c3912883faa9287fb7 by GitHub (on behalf of A. Jiang) on 28/07/2026 at 11:42..
[libc++][test][NFC] Format `test_macros.h` (#212442)

Avoiding errors about untouched lines from clang-format when modifying
conditions in `test_macros.h`.
https://invent.kde.org/qt/clang/llvm-project/-/commit/abd3b3a1445b5a8eeffae5c3912883faa9287fb7

Git commit 391d298c2ae471c28e7db8538d867a017f9d08df by GitHub (on behalf of Zichen Lu) on 28/07/2026 at 11:52..
[mlir][Target] Make nvptxcompiler passed options high priority to keep consistent with ptxas behavior (#121036)

When using `ptxas` to do ptx->cubin, the options passed (via `cmd`) have
higher priority than the gpuModule target (such as `opt-level`). When
using `nvptxcompiler`, it is the opposite and we need to be consistent.
https://invent.kde.org/qt/clang/llvm-project/-/commit/391d298c2ae471c28e7db8538d867a017f9d08df

Git commit f11d740e204f0551ac72ab1a2cacd72ae5c41b26 by GitHub (on behalf of Pavel Labath) on 28/07/2026 at 12:11..
[libc] Make hash_test hermetic (#212428)

Aligned allocation is now supported, but the test burns through our 1MB
never-freeing bump pointer allocation buffer. I tweak the test to reuse
the buffer between loop iterations, reducing its memory usage by about
300x :P.
https://invent.kde.org/qt/clang/llvm-project/-/commit/f11d740e204f0551ac72ab1a2cacd72ae5c41b26

Git commit 2a50c95322bc0ff3bbd976564914ce297b251a1a by GitHub (on behalf of Jameson Nash) on 28/07/2026 at 12:12..
Thread Safety Analysis: Honor try-lock branches of a void conditional (#211973)

Try-locks are not acquired on the arms of a `?:`, because the arms would
then disagree about whether the capability is held and warn where they
join. That reasoning assumes the `?:` produces a result that is branched
on later, which is where the acquisition is handled instead.

A void `?:` has no such result. Its branch is all there is to interpret,
and its arms might not join at all because one of them does not return
(this is how glibc before 2.32 spells `assert()`).

So asserting that a try-lock succeeded left the capability unheld on
every path, and a function documented to acquire it warned that it did
not, if written like so:

  void lock(void) ACQUIRE(mu) {
    int got = trylock();
assert(got); // warning: expecting mutex 'mu' to be held at the end of
function
  }

Only bail out for a `?:` that has a result to be used, so that a void
`?:` acquires on its branch like any other terminator (for example,
including `&&` and `||`).

Assisted-by: Claude Opus 5
https://invent.kde.org/qt/clang/llvm-project/-/commit/2a50c95322bc0ff3bbd976564914ce297b251a1a

Git commit ac8b30c74b595dd8dfa612912663e57dafcf3355 by GitHub (on behalf of A. Jiang) on 28/07/2026 at 12:22..
[libc++][test] Suppress warning on bitwise shift with `bool` operands in `std::byte` tests for MSVC (#212433)

It was intentional in https://llvm.org/PR204116 that tests for
`operator<<`, `operator<<=`, `operator>>`, `operator>>=` used `bool`
operands, because `bool` is an integral type and thus satisfies the
constraints of these operators.

However, MSVC considers `bool` is unsafe as an operand of bitwise shift
operators and emits warning C4804. So this patch suppresses the warning
for MSVC.
https://invent.kde.org/qt/clang/llvm-project/-/commit/ac8b30c74b595dd8dfa612912663e57dafcf3355

Git commit c273220275a7cbb8384812e1a4c84e773e1dd820 by GitHub (on behalf of Arseniy Obolenskiy) on 28/07/2026 at 12:25..
[mlir][SCFToSPIRV] Fix iter_args returning undef on zero trip scf.for (#206280)
https://invent.kde.org/qt/clang/llvm-project/-/commit/c273220275a7cbb8384812e1a4c84e773e1dd820

Git commit 584734513c63b309b46a945cddbf0a516a9d133c by GitHub (on behalf of Lang Hames) on 28/07/2026 at 12:28..
[ORC] Drop ExecutorProcessControl::JITDispatchInfo. (#212434)

The JIT-dispatch mechanism lets JIT'd code call handlers in an ORC
ExecutionSession, via the "__orc_rt_jit_dispatch" and
"__orc_rt_jit_dispatch_ctx" symbols. Until now ExecutorProcessControl
carried the addresses backing those symbols in a dedicated
JITDispatchInfo struct, which every EPC had to populate and each
Platform read back to define the symbols.

That detour couples ExecutorProcessControl to the shape of the dispatch
mechanism -- two symbols with fixed names -- and forces every EPC to
provide the addresses whether or not a given JIT setup uses dispatch.

Represent the two addresses as ordinary bootstrap symbols instead. EPCs
that support dispatch add __orc_rt_jit_dispatch(_ctx) to their bootstrap
symbols; Platforms reexport them from the bootstrap JITDylib rather than
reading JITDispatchInfo. EPCs that don't use dispatch provide nothing,
and ExecutorProcessControl no longer references the mechanism at all.
https://invent.kde.org/qt/clang/llvm-project/-/commit/584734513c63b309b46a945cddbf0a516a9d133c

Git commit 8c8cc1cfb9f04fc57716b9ccc3ea74c9a5495bf7 by GitHub (on behalf of Akash Agrawal) on 28/07/2026 at 12:28..
[Clang][Parse] Fix assertion when annotating a failed decltype-specifier (#211221)

`ParseDeclaratorInternal's` member-pointer special case enters a
speculative scope-specifier parse whenever it sees `decltype`, without
checking that `( `follows:


```
if (getLangOpts().CPlusPlus &&
    (Tok.is(tok::coloncolon) || Tok.is(tok::kw_decltype) || ...)) {
```
But `decltype-specifier` is always `decltype ( expression ) — decltype`
not followed by `(` can never be valid. When that happens,
`ParseOptionalCXXScopeSpecifier` still tries to parse it as one, fails,
and error recovery skips tokens. The EndLoc returned is then stale by
the time `AnnotateExistingDecltypeSpecifier` uses it to annotate, which
trips the invariant in `Preprocessor::AnnotatePreviousCachedTokens`:


```
int decltype;      // crashed
int *decltype = 0; // crashed
```
Fix: only take this path when decltype is followed by (.


`(Tok.is(tok::kw_decltype) && NextToken().is(tok::l_paren)) ||`

`ParseDecltypeSpecifier` already requires `(` right after `decltype` or
bails with `TST_error`, so this check drops no valid parse —
`decltype(expr)` (including as a member-pointer scope, e.g.` int
decltype(obj)::*p = &S::m;) `is unaffected.

Fixes #211207

Co-authored - Claude-Sonnet
https://invent.kde.org/qt/clang/llvm-project/-/commit/8c8cc1cfb9f04fc57716b9ccc3ea74c9a5495bf7

Git commit ad6cb6dedc9dc1d965d60e1a34289c2bb30e7cec by GitHub (on behalf of Nikita Taranov) on 28/07/2026 at 12:36..
[X86] Reapply #210739 with a fix (#212020)

This reapplies #210739, which was reverted in #211958 because it could
crash the backend with "Invalid rip-relative address" when an LEA added
a RIP-relative global and an already-materialized value.

Fixes #51707
https://invent.kde.org/qt/clang/llvm-project/-/commit/ad6cb6dedc9dc1d965d60e1a34289c2bb30e7cec

Git commit 9572596c3951a5fef5eecc011c617c1b264357b7 by GitHub (on behalf of Paul Walker) on 28/07/2026 at 12:45..
[LLVM][CodeGen] Clean up uses of useSVEForFixedLengthVectorVT(). (#211605)

During lowering `useSVEForFixedLengthVectorVT` only serves to separate
NEON sized vectors from those made legal for SVE VLS. When no separation
is required there is no reason to call the function. That means
`useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true)` is largely
synonymous to `isSVEorStreamingSVEAvailable()`.
    
`useSVEForFixedLengthVectorVT` is not a per operation property. For this
reason I have removed the AllowBF16 parameter and replaced it by a
command line option that can be used during SVE VLS bfloat bringup. The
one existing use has been removed because it falls under the previous
issue in there being no need to call `useSVEForFixedLengthVectorVT`.
https://invent.kde.org/qt/clang/llvm-project/-/commit/9572596c3951a5fef5eecc011c617c1b264357b7

Git commit c154f4aa5483915702d8447d541d5d9a4dfaac46 by GitHub (on behalf of Matt Arsenault) on 28/07/2026 at 13:09..
AMDGPU: Remove dead FEATURE_FP64/FEATURE_LDEXP from ArchFeatureKind (#212479)

No GPU ever sets these bits, and clang's hasFP64()/hasLDEXPF()
short-circuit on isAMDGCN() before testing them, so the bits are 
never observed.

Co-authored-by: Claude (Claude-Opus-4.8)
https://invent.kde.org/qt/clang/llvm-project/-/commit/c154f4aa5483915702d8447d541d5d9a4dfaac46

Git commit e432cb12962f1619bc73c50a2dc4d2ad5ac6b44c by GitHub (on behalf of Natanael Cintean) on 28/07/2026 at 13:11..
[mlir]Add resultSegmentSizes/operandSegmentSizes to prop-dict. (#211222)

`setPropertiesFromParsedAttr` (generated by `OpFormatGen.cpp` for ops
using a custom `assemblyFormat`) rejects the trait-injected
`operandSegmentSizes` /. `resultSegmentSizes` properties when they
appear in a `prop-dict`, even though the printer emits them there for ops
whose format uses a bulk operand/result type directive
(`type(operands)`, `type(results)`, `functional-type(operands, results)`).

This breaks round-tripping: any op combining `AttrSizedOperandSegments`
/ `AttrSizedResultSegments` with such a bulk directive fails to re-parse
its own printed output, because printer-side elision of these keys
(introduced in #115930) is intentionally skipped in that case — the
sizes can't be reconstructed from individually-typed operand/result 
groups, so they must survive in the text, but the custom parser was never
taught to read them back.

`setPropertiesFromAttr` (used by the generic-form parser, bytecode, and
C++ construction) already special-cases these two keys, so this change
makes `setPropertiesFromParsedAttr` mirror that behavior: keys are
accepted from the dictionary attr when the corresponding trait is present,
and required exactly when the format can't reconstruct the sizes itself
(i.e. when `fmt.allOperands` / `fmt.allResultTypes` is true). Otherwise the
key remains optional, since `genParserVariadicSegmentResolution`
overwrites it with the sizes inferred from the parsed operand/result
groups.

The contents of the PR as well as description has been made using
github-copilot. However I've reviewed the contents and tested locally
the change.

Fixes #211220
https://invent.kde.org/qt/clang/llvm-project/-/commit/e432cb12962f1619bc73c50a2dc4d2ad5ac6b44c

Git commit 89d39f69cb18f21d92b261cc0ca2a2314453b1fe by GitHub (on behalf of Yingwei Zheng) on 28/07/2026 at 13:18..
[SimplifyCFG] Bail out on trivial cases in `mergeNestedCondBranch` (#212309)

Closes https://github.com/llvm/llvm-project/issues/212300.

When BB3 is identical to BB4, it is no longer profitable to perform this
fold, since it creates an unused xor instruction. The DomTree update
issue is also easy to fix. But I think this solution is better.

The following IR was dumped just before this function:
```
define void @func(i1 %cond1, i1 %cond2, i1 %cond3) {
entry:
  br i1 %cond1, label %bb2, label %else

else:                                             ; preds = %entry
  br i1 %cond2, label %bb0, label %common.ret

bb0:                                              ; preds = %else
  br i1 %cond1, label %bb1, label %bb2

bb2:                                              ; preds = %bb0, %entry
  br i1 %cond3, label %common.ret, label %common.ret

bb1:                                              ; preds = %bb0
  br i1 %cond3, label %common.ret, label %common.ret

common.ret:                                       ; preds = %bb2, %bb1, %bb2, %bb1, %else
  ret void
}
```
The previous functions will simplify it. So the reproducer cannot be
further reduced.
https://invent.kde.org/qt/clang/llvm-project/-/commit/89d39f69cb18f21d92b261cc0ca2a2314453b1fe

Git commit 857746b37949a87faa42faff4fae12c35b34db51 by GitHub (on behalf of Matt Arsenault) on 28/07/2026 at 13:27..
AMDGPU: Fix missing extended-image-insts missing from feature map (#212418)

Unsurprisingly, this manually maintained table is buggy.
fillAMDGCNFeatureMap never set extended-image-insts, so clang's builtin
feature check rejected every case. The tests were working around this
with manually specified -target-features flags.

Co-authored-by: Claude (Claude-Opus-4.8)
https://invent.kde.org/qt/clang/llvm-project/-/commit/857746b37949a87faa42faff4fae12c35b34db51

Git commit 34be3a62bf9a309fb00a4a2ec2150fa87750ad96 by GitHub (on behalf of Alex Duran) on 28/07/2026 at 13:40..
[OFFLOAD][L0][NFC] Mark as skip unittest with driver issue (#212466)
https://invent.kde.org/qt/clang/llvm-project/-/commit/34be3a62bf9a309fb00a4a2ec2150fa87750ad96

Git commit 8d632c0a8eef06b7be509d10a6d87c9bd814a10e by GitHub (on behalf of Akshay K) on 28/07/2026 at 13:45..
[X86] Don't clobber x87 return values when zeroing call-used registers (#211129)

### Summary
`-fzero-call-used-regs=all` / `zero_call_used_regs("all")`
unconditionally push eight `fldz` onto the x87 stack before returning.
When a value is live in `ST0` (`long double`) or `ST0:ST1` (`_Complex
long double`), the pushes overflow the 8-slot x87 stack and the return
value becomes an indefinite NaN. Reproduces on x86-64 at every
optimization level, via both the flag and the attribute.

```c++
__attribute__((zero_call_used_regs("all")))
long double g(long double a) { return a + 1; }
// g(1.0L) returns nan, expected 2.0
```

### Root cause
The x87 return value lives in `ST0` (and `ST1` for `_Complex long
double`), but the FP stackifier's `handleReturn` deletes the `RET`'s FP
register operands after stackification (the `FP0`-`FP6` pseudos no
longer exist) without recording that the top of the x87 stack is live.
The scrub in `emitZeroCallUsedRegs` therefore has nothing telling it
`ST0` is occupied, so it pushes a zero over the return value.

### Fix
`handleReturn` now re-records the returned values as implicit
`ST0`/`ST1` uses on the return instruction — the same way every other
return register (`RAX`, `XMM0`, ...) is modeled — and
`emitZeroCallUsedRegs` pushes only `8 - live` zeros, filling the dead
slots and leaving the return value intact. This matches GCC.

Note: the implicit `ST0`/`ST1` operands are recorded on every
x87-returning `RET`, not only under `zero-call-used-regs`. One
consequence is that a `RET` now satisfies `isX87Instruction`, so
`X86InsertX87Wait` is adjusted so a return no longer suppresses the
strict-FP `wait` (a return performs no exception sync).

### Secondary fix (i386)
The old count was hardcoded `ST.is64Bit() ? 8 : 7`. On i386, a function
with no x87 value live at the return (e.g. an integer return) cleared
only seven of the eight physical x87 registers, so `"all"` silently left
one call-used register uncleared. The unified `8 - live` formula fixes
this too: i386 with no x87 return now pushes 8 (previously 7).

### Tests
`zero-call-used-regs.ll` adds `all_x87_return` (`x86_fp80`, 1 live -> 7
pushes), `all_x87_complex_return` (`_Complex long double`, 2 live -> 6
pushes), and `all_no_x87_live` (no x87 live -> 8 pushes, guarding the
i386 secondary fix). The full X86 CodeGen suite passes.

Fixes #211064

Assisted-by: Cursor
https://invent.kde.org/qt/clang/llvm-project/-/commit/8d632c0a8eef06b7be509d10a6d87c9bd814a10e

Git commit 2c01f3cb3caf2dfcdcd65ced4ec124a672465cb5 by GitHub (on behalf of Sohaib Iftikhar) on 28/07/2026 at 14:12..
[BUILD]Fixes 9a543446 (#212499)

[BUILD]Fixes 9a543446
https://invent.kde.org/qt/clang/llvm-project/-/commit/2c01f3cb3caf2dfcdcd65ced4ec124a672465cb5

Git commit 3d325269ece14bfb98af65443c8d345d6434bdee by GitHub (on behalf of Nick Sarnie) on 28/07/2026 at 14:15..
[offload][lit] Run check-offload as part of check-all (#212500)

It's unclear why these were excluded from `check-all`, but we made all
tests pass on Level Zero and our local testing shows they pass on AMD
and NVIDIA too, so enable it by default.

Context: https://github.com/llvm/llvm-project/pull/211633

Signed-off-by: Nick Sarnie <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/3d325269ece14bfb98af65443c8d345d6434bdee

Git commit 7d4160e52ba0e06d1450fa8e9c31518c0e58895c by GitHub (on behalf of Frederik Harwath) on 28/07/2026 at 14:16..
[AMDGPU] Stop rounding up LDS block size for gfx950 (#208046)

The AMDGPUAsmPrinter::getSIProgramInfo function calculates the number of
LDS blocks in a somewhat indirect way: It obtains the LDS granularity
from another function, determines an "LDSAlignShift" based on this and
then uses shifts to determine the alignment and for division. The use of
shifts forces the alignment to be a power of two which works for all LDS
granularity values except for the value of 1280 bytes used for gfx950.
For this, the function uses LDSAlignShift = 11 which means that the
block size gets rounded up to 2048. This implies that the computed
number of LDS blocks is too small.

Remove the use of LDSAlignShift from getSIProgramInfo and use the LDS
granularity directly for alignment and division.
https://invent.kde.org/qt/clang/llvm-project/-/commit/7d4160e52ba0e06d1450fa8e9c31518c0e58895c

Git commit 298355525c28343fecdee28b0cf75c8d94e96952 by GitHub (on behalf of Yaxun (Sam) Liu) on 28/07/2026 at 14:19..
[HIP] Support device-only linking of bitcode offload binaries (#212342)

The new offload driver packages multi-architecture bitcode in LLVM
offload binaries. A later `--hip-link --offload-device-only`
invocation treated these `.bc` inputs as host LLVM IR and dropped
them before linking.

Pass these inputs directly to clang-linker-wrapper when producing a
device fat binary. The wrapper can then extract and link each
requested GPU architecture.
https://invent.kde.org/qt/clang/llvm-project/-/commit/298355525c28343fecdee28b0cf75c8d94e96952

Git commit b976ce0867d1f828863c61899c5d779f2bd4bfff by GitHub (on behalf of Nick Sarnie) on 28/07/2026 at 14:22..
Revert "[offload][lit] Run check-offload as part of check-all" (#212506)

Reverts llvm/llvm-project#212500
https://invent.kde.org/qt/clang/llvm-project/-/commit/b976ce0867d1f828863c61899c5d779f2bd4bfff

Git commit 56fd82467c5b5a98411c02df1957528aaf57b487 by GitHub (on behalf of Matt Arsenault) on 28/07/2026 at 14:24..
AMDGPU: Migrate verifier tests to subarch triples (#212494)
https://invent.kde.org/qt/clang/llvm-project/-/commit/56fd82467c5b5a98411c02df1957528aaf57b487

Git commit 55076d312e30e28c9440fc25b9e60bb7764c1540 by GitHub (on behalf of Matt Arsenault) on 28/07/2026 at 14:25..
AMDGPU: Migrate asan tests to subarch triples (#212496)
https://invent.kde.org/qt/clang/llvm-project/-/commit/55076d312e30e28c9440fc25b9e60bb7764c1540

Git commit 455ef3684fae3273b3423bb0229e33584745c6cc by GitHub (on behalf of Nikolas Klauser) on 28/07/2026 at 14:27..
[libc++] Fix ungetc failing after xsgetn (#210951)

After #206453 we don't correctly handle `unget()` anymore. This fixes
the issue by updating the internal buffer to contain the tail of the
read data.

Fixes #210203
https://invent.kde.org/qt/clang/llvm-project/-/commit/455ef3684fae3273b3423bb0229e33584745c6cc

Git commit 371b78a9638d4fcea397af5a318b1f3d562b20fa by GitHub (on behalf of Matt Arsenault) on 28/07/2026 at 14:27..
AMDGPU: Migrate assembler tests with content changes to subarch triples (#212495)

Convert tests which failed after converting the arguments due to content
changes from checking the emitted target id string.
https://invent.kde.org/qt/clang/llvm-project/-/commit/371b78a9638d4fcea397af5a318b1f3d562b20fa

Git commit 5a650306e4e1069d194d8fcfeee821d7e424f9b3 by GitHub (on behalf of Srividya Sundaram) on 28/07/2026 at 14:31..
[Driver][SYCL] Add compile-time device library linking for SPIR-V targets (#196656)

This PR implements compile-time device library linking for SYCL
offloading to SPIR-V targets, using `libclang_rt.builtins.bc` - an
in-tree compiler-rt artifact produced alongside the existing
`libclang_rt.builtins.a` for `SPIRV64`.

## Motivation

SYCL device compilations targeting SPIR-V need access to compiler
builtins (integer arithmetic, floating-point helpers, etc.) at compile
time so the compiler can optimize across user code and builtins, inline
aggressively, and eliminate dead code. This PR lays the foundation by
wiring up the first in-tree device library : `libclang_rt.builtins.bc` -
using the same `-mlink-builtin-bitcode` mechanism already used by
`libclc` and `HIP`.

## Changes

**compiler-rt (compiler-rt/lib/builtins/CMakeLists.txt)**
For the `spirv64` target, after building
`libclang_rt.builtins-spirv64.a`, runs `llvm-link` to merge all bitcode
objects into a single `libclang_rt.builtins.bc`. This file is installed
to `<ResourceDir>/lib/spirv64-unknown-unknown/` alongside the static
archive. The `-mlink-builtin-bitcode` flag requires raw LLVM IR and
cannot unpack a static archive directly, hence the extra step.

**Clang Driver (clang/lib/Driver/ToolChains/SYCL.cpp)**
`SYCLToolChain::getDeviceLibs()` now constructs the path to
`libclang_rt.builtins.bc` under the clang resource directory and returns
it for `-mlink-builtin-bitcode` injection during `spirv64` device
compilation. If the file is absent (e.g. compiler-rt was not built with
spirv64 support), a specific diagnostic is emitted. Linking is
suppressed when `--no-offloadlib` is passed.

**Diagnostics (clang/include/clang/Basic/DiagnosticDriverKinds.td)**
Added `err_drv_no_compiler_rt_builtins_bc`, following the
`err_drv_libclc_not_found` community pattern, with actionable guidance
on how to build compiler-rt with SPIR-V support.


### Test Infrastructure

1. `clang/test/Driver/sycl-device-lib-spirv64.cpp` - new test verifying
-mlink-builtin-bitcode is passed for spirv64, suppressed with
--no-offloadlib, and that a missing .bc produces the correct diagnostic.
2. `clang/test/Driver/Inputs/spirv64-sycl/` - dummy resource-dir fixture
used by driver tests.
3. All existing SYCL driver tests updated to pass -`resource-dir
%S/Inputs/spirv64-sycl `on -fsycl RUN lines, making them independent of
the installed clang resource directory on CI runners.

## Behavior

### Default

```bash
clang -fsycl myprogram.cpp
# Device compilation includes:
# "-mlink-builtin-bitcode" "<ResourceDir>/lib/spirv64-unknown-unknown/libclang_rt.builtins.bc"
```

Automatically links device libraries from `<clang-install>/lib/` during
device compilation.

### Without device libraries
```bash
clang -fsycl --no-offloadlib myprogram.cpp
# -mlink-builtin-bitcode is suppressed
```
Missing .bc (compiler-rt not built with spirv64 support)
```bash
error: no compiler-rt builtins bitcode library '...' found in the clang resource directory;
build compiler-rt with SPIR-V support or pass '--no-offloadlib' to compile without it ```
https://invent.kde.org/qt/clang/llvm-project/-/commit/5a650306e4e1069d194d8fcfeee821d7e424f9b3

Git commit e362f3c8466dfb4021d409f50eae179b9b0b1957 by GitHub (on behalf of Jeff Bailey) on 28/07/2026 at 14:35..
[libc][stdlib] Add putenv (#208339)

Added the POSIX putenv() function and its internal support.

Implemented EnvironmentManager::put() to insert caller-provided
"name=value" strings directly into the environment array, managing
ownership correctly (caller retains ownership).

Registered for x86_64, aarch64, and riscv. Integration tests cover basic
operations, ownership semantics, validation, and edge cases.

Assisted-by: Automated tooling, human reviewed.
https://invent.kde.org/qt/clang/llvm-project/-/commit/e362f3c8466dfb4021d409f50eae179b9b0b1957

Git commit 7cf62f99cd707d09f4dab5f999cb1ce5d57d25a5 by GitHub (on behalf of Jeff Bailey) on 28/07/2026 at 14:37..
[libc] Add POSIX redirection header specifications in YAML (#211859)

Add header YAML specifications for memory.h, sys/poll.h, sys/unistd.h,
sys/fcntl.h, and sys/signal.h using public_includes.

POSIX.1-2017 and historical X/Open System Interfaces (XSI) standards
define these headers as alternate or legacy header locations that
forward to string.h, poll.h, unistd.h, fcntl.h, and signal.h
respectively. The YAML header specs allow hdrgen to generate the public
headers automatically with proper license headers and guards.

Updated Linux target headers.txt configuration files to register the new
public header targets for installation.

Assisted-by: Automated tooling, human reviewed.
https://invent.kde.org/qt/clang/llvm-project/-/commit/7cf62f99cd707d09f4dab5f999cb1ce5d57d25a5

Git commit 557dcec6258aac87f9c2bb6d651ec7e774f7d09d by GitHub (on behalf of Luke Lau) on 28/07/2026 at 14:49..
[VE] Fix crash when splitting all-ones v512i1 mask (#212489)

The added test case crashes because we try to extract a subreg from vmp0
when selecting vec_unpack_*, but vmp0 has no subregisters, see
d46e49838e17800cb72d95db1b23c04bbca610e2

vmp0 is hardwired to all ones, so it gets selected for an all ones mask.

Fix it by adding an explicit pattern for an all ones mask that selects
vm0, the v256i1 version of vmp0, instead of creating an invalid subreg
extract.
https://invent.kde.org/qt/clang/llvm-project/-/commit/557dcec6258aac87f9c2bb6d651ec7e774f7d09d

Git commit b6b9603c7675fff5ec9befacf54391a516fc723c by GitHub (on behalf of Paschalis Mpeis) on 28/07/2026 at 14:52..
[RFC][BOLT] Enable lite mode by default on AArch64 (#205545)
https://invent.kde.org/qt/clang/llvm-project/-/commit/b6b9603c7675fff5ec9befacf54391a516fc723c

Git commit 760fc017332d4d5a5cdf1b6cf754f40774a97821 by GitHub (on behalf of Nick Sarnie) on 28/07/2026 at 14:53..
[offload][lit] Run check-offload-unit as part of check-all (#212513)

I tried to do `check-offload` instead but that
[caused](https://github.com/llvm/llvm-project/pull/212500) a bloodbath,
so just enable `check-offload-unit` as part of `check-all`.

Signed-off-by: Nick Sarnie <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/760fc017332d4d5a5cdf1b6cf754f40774a97821

Git commit 034f0f1ad4badc02d9d26b6f1ae3324a09276c4a by GitHub (on behalf of Eugene Epshteyn) on 28/07/2026 at 14:59..
[flang] Stop running array-value-copy in the default pipeline (#211816)

Since the removal of the legacy expression lowering (#210385, #210621,
#210639, #210873), nothing in flang produces the array-value operations
(fir.array_load and friends) that the array-value-copy pass legalizes,
so the pass runs as a guaranteed no-op on every function. Remove it from
the default pipeline (addAVC and the disable-avc mlir option); the pass
itself and its fir-opt tests remain and still run via fir-opt
--array-value-copy.

The array-value operations themselves and the pass are planned for
removal in follow-up patches.

flang/test/Fir/arrexp.fir is deleted rather than updated: it feeds
legacy array-value ops through tco's full pipeline, which no longer
legalizes them (the ops have no codegen patterns), and the file
exercises no live feature beyond that legalization.

Assisted-by: AI
https://invent.kde.org/qt/clang/llvm-project/-/commit/034f0f1ad4badc02d9d26b6f1ae3324a09276c4a

Git commit 807de2dc44794205b336ed8b2ca4731bc3ab865b by GitHub (on behalf of Arseniy Obolenskiy) on 28/07/2026 at 15:01..
[AMDGPU] Stop iDot4 chain walker at non-ADD nodes (#198412)

The loop body in performAddCombine dot4 matcher unconditionally treats
TempNode operands as the next link's addends, so the chain only works
when TempNode is an `ISD::ADD`

The old getNumOperands() guard let AND/OR/XOR/etc. through, leaking
their non-addend operands (e.g. a constant mask) into the dot4
accumulator and miscompiling kernels
https://invent.kde.org/qt/clang/llvm-project/-/commit/807de2dc44794205b336ed8b2ca4731bc3ab865b

Git commit 1c31d28d1a1e746db9070c90ff40f8a6f53ff0db by GitHub (on behalf of Sirui Mu) on 28/07/2026 at 15:03..
[CIR] Disallow mem2reg for volatile/atomic loads and stores (#212262)

Current mem2reg implementation for `cir.load` and `cir.store` does not
check whether the load/store is volatile or atomic. Fix this.
https://invent.kde.org/qt/clang/llvm-project/-/commit/1c31d28d1a1e746db9070c90ff40f8a6f53ff0db

Git commit df89bcad92cd1a8539d85b200e89182f26743b6f by GitHub (on behalf of Kevin Bravo) on 28/07/2026 at 15:08..
[TableGen] Treat carriage return as line end in prepSkipRegion (#212411)

`prepSkipRegion` currently only treats newline and EOF as end of line.
However, in the TableGen Programmer's Reference:

LineEnd ::=  newline | return | EOF

So carriage return is a valid end-of-line, but `prepSkipRegion` ignores
it and skips code after the carriage return that it shouldn't. This
change fixes the end-of-line check in `prepSkipRegion` so that it also
treats carriage return as end of line.

Related issue: #151476.
https://invent.kde.org/qt/clang/llvm-project/-/commit/df89bcad92cd1a8539d85b200e89182f26743b6f

Git commit 126447232820c207b88f4687fab34a68c0b03445 by Petar Avramovic on 28/07/2026 at 16:18..
AMDGPU/GlobalISel: Fix Vcc reg bank apply method for sgpr i1 input

Need to clean up high bits on sgpr bool use, simlar to Sgpr32AExtBoolInReg.
G_AMDGPU_COPY_VCC_SCC assumes clean (zero) high bits in sgpr i32 input.
This should be combined away in most cases, for example if input is result
of a compare. But should stay for example for truncated input from s_load.
https://invent.kde.org/qt/clang/llvm-project/-/commit/126447232820c207b88f4687fab34a68c0b03445