[qt/clang/llvm-project]: Summary of bulk changes made

Git repository change summary for qt/clang/llvm-project
Pushed by mirror-service into branch 'upstream/users/arsenm/clang-amdgpu-forward-xnack-sramecc-to-assembler'.
Changed from 0000000000000000000000000000000000000000 to a4b3c7eb161ecb1fcf73a46061871aa69589cfc1
Acknowledgement was received that this change introduces only existing code that has been pushed to another public open source repository.

This change contains the following new commits:

Git commit e1f93b045410f3872d3524d91d71ba5eceda0030 by GitHub (on behalf of Matt Arsenault) on 30/07/2026 at 05:28..
MSP430: Mark more generic libgcc functions as available (#212927)

The generic soft-float, conversion, comparison and integer helper
routines (__addsf3, __divli's __divsi3, __ashlsi3, ...) exist in the
MSP430 libgcc port alongside the preferred __mspabi_* variants. They 
were previously removed to force selection of the __mspabi_* names, back 
when only one implementation per libcall could be recorded.

Stop hiding them: only __lshrsi3 stays excluded, since the MSP430 libgcc
port provides the 32-bit logical right shift solely under __mspabi_srll
and never defines a generic __lshrsi3.

Repost of #210962

Co-authored-by: Claude (Claude-Opus-4.8) <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/e1f93b045410f3872d3524d91d71ba5eceda0030

Git commit 7330a8ddc106483031a67d5a74215fc3e1509905 by GitHub (on behalf of Matt Arsenault) on 30/07/2026 at 05:42..
AMDGPU: TableGen subarch to major subarch table (#212605)

Replace the hand-written AMDGPUMajorFamilies array with a
generated lookup table. Adds a special case for the major
arches missing a concrete generic target definition (we probably
should just define those to avoid this).

Co-authored-by: Claude (Claude-Opus-4.8)
https://invent.kde.org/qt/clang/llvm-project/-/commit/7330a8ddc106483031a67d5a74215fc3e1509905

Git commit 26d08c22c68bbb9e644012c4e5cae32f68d897cb by GitHub (on behalf of saloni-shinde-Q) on 30/07/2026 at 05:53..
[RISCV][MC] Improve FPR Error Messages (#212492)

This patch improves the error messages for the following register classes:
    
   1. FPR RegClasses (FPR16, FPR32, FPR64, FPR128, FPR256)
   2. Compressed FPR RegClasses (FPR16C, FPR32C, FPR64C)
   3. GPR-as-FPR classes used by Zfinx/Zdinx extensions (GPRAsFPR16, GPRAsFPR32, GPRF64AsFPR, GPRPairAsFPR).

---------

Co-authored-by: Saloni Shinde <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/26d08c22c68bbb9e644012c4e5cae32f68d897cb

Git commit b42621f842571a92cec2961fa5c4fc518d4ca91a by GitHub (on behalf of Matt Arsenault) on 30/07/2026 at 06:50..
AMDGPU: TableGen the subarch to processor name mapping table (#212606)

Replace the hand-written AMDGPUSubArchNames array (SubArch -> canonical
GPU name) with a generated table.

Co-authored-by: Claude (Claude-Opus-4.8)
https://invent.kde.org/qt/clang/llvm-project/-/commit/b42621f842571a92cec2961fa5c4fc518d4ca91a

Git commit 23a22244b099a9950a5f265460e392bc44beb3b4 by GitHub (on behalf of Pengcheng Wang) on 30/07/2026 at 06:50..
[RISCV][MC] Support experimental Zilx extension

This adds the MC support for `Zilx` (Indexed Integer Load Instructions)
extension.

Doc: https://github.com/riscv/riscv-zilx

Reviewers: topperc, tclin914, kito-cheng

Pull Request: https://github.com/llvm/llvm-project/pull/209419
https://invent.kde.org/qt/clang/llvm-project/-/commit/23a22244b099a9950a5f265460e392bc44beb3b4

Git commit 8a1ff7feefc5825cc10349b8946fe555f435d53b by GitHub (on behalf of Pengcheng Wang) on 30/07/2026 at 06:52..
[RISCV] Support CodeGen of Zilx extension

Thanks for `XTheadMemIdx` extension that makes life easier.

Reviewers: lukel97, topperc, kito-cheng, tclin914

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/209420
https://invent.kde.org/qt/clang/llvm-project/-/commit/8a1ff7feefc5825cc10349b8946fe555f435d53b

Git commit b84c5f4abcfb464e362bcd2b8eb58ef96ecbae9d by GitHub (on behalf of Fangrui Song) on 30/07/2026 at 07:16..
[BFI] Simplify/optimize getMass/getContainingLoop. NFC (#212938)

A block can head both a natural loop and the irreducible loop wrapping
it (`@crossloops` in BlockFrequencyInfo/irreducible.ll).

getContainingLoop and getMass unroll to a fixed depth of two through
isDoubleLoopHeader and isADoublePackage.  Depth two holds because
IrreducibleGraph::addEdge drops edges into the enclosing loop's headers,
keeping such a header out of any nested SCC.

(The old comment "If it's a node inside a packaged loop, it returns the
loop's mass." is wrong.)

Walk the Parent chain instead to drop the depth two assumption. Testing
`IsPackaged` before isHeader also skips the Nodes[0] load on the common
path.
https://invent.kde.org/qt/clang/llvm-project/-/commit/b84c5f4abcfb464e362bcd2b8eb58ef96ecbae9d

Git commit de26036ecb4b450e5e1bdc49ee7101e3ce294bc4 by GitHub (on behalf of Matt Arsenault) on 30/07/2026 at 07:36..
AMDGPU: Eliminate old macro driven processor name parsing (#212608)

Previously the generated inc file had a series of macros for use
with StringSwitch; now just directly scan the generated name table.

Co-authored-by: Claude (Claude-Opus-4.8)
https://invent.kde.org/qt/clang/llvm-project/-/commit/de26036ecb4b450e5e1bdc49ee7101e3ce294bc4

Git commit f08211e71e8fec39ff64facef84cb104ea8119e7 by GitHub (on behalf of Cullen Rhodes) on 30/07/2026 at 07:43..
[AArch64] Remove assembler-only register classes (#211527)

ZPRMul2, ZPRMul4 and PPRMul2 register classes are used solely by the asm
parser to validate other register classes (ZPR2Mul2, ZPR4Mul4,
PPR2Mul2). Since they're real register classes TableGen synthesizes
numerous intersection classes and pressure sets from them.

Removing them and validating the constraint directly in the assembly
parser reduces:

- generated register classes: 521 -> 403 (~22%)
- generated pressure sets: 188 -> 60 (68%)
- generated register-info size: 11.9 MB -> 9.1 MB (23%)

Also improves CTMark geomean -0.23% on stage1-aarch64-O3.

https://llvm-compile-time-tracker.com/compare.php?from=a90dbb43cd67856f681feba82d51a0d5fbcae3c2&to=5565d4907cdf960cc142a7507f16e551f51919b0&stat=instructions%3Au

Assisted-by: codex
https://invent.kde.org/qt/clang/llvm-project/-/commit/f08211e71e8fec39ff64facef84cb104ea8119e7

Git commit fc764a7c2b12c508c72e04a606dd2d2c815e2d94 by GitHub (on behalf of Matt Arsenault) on 30/07/2026 at 07:55..
ARM: Mark more generic libgcc functions as available (#210961)

Generic libgcc/compiler-rt functions coexist with aeabi variants
(e.g., __divsi3  and __aeabi_idiv) according to my reading of the
build. At least in compiler-rt, some are aliases.

They were previously removed from the available set on AEABI+AAPCS
targets to force selection of the preferred __aeabi_* variants, back when
only one implementation per libcall could be recorded.

Now that multiple implementations can be available per libcall, stop
hiding the generics and select the __aeabi_* variant explicitly as the
preferred implementation. This reduces the number of special cases to 
consider for future libcalls info improvements.

Co-authored-by: Claude (Claude-Opus-4.8) <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/fc764a7c2b12c508c72e04a606dd2d2c815e2d94

Git commit a4b3c7eb161ecb1fcf73a46061871aa69589cfc1 by Matt Arsenault on 30/07/2026 at 08:28..
clang/AMDGPU: Forward xnack/sramecc mode to the assembler

When assembling a .s file with no target ID directive, the requested
xnack/sramecc mode has no module flag to carry it. Forward the mode
requested via -mxnack/-msramecc (or the -mcpu target ID modifiers) to the
assembler as a target feature so it is recorded in the object's e_flags.

Co-authored-by: Claude (Opus 4.8) <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/a4b3c7eb161ecb1fcf73a46061871aa69589cfc1