[qt/clang/llvm-project]: Summary of bulk changes made

Git repository change summary for qt/clang/llvm-project
Pushed by mirror-service into branch 'upstream/users/gandhi56/globalisel/remove-redundant-and-shift'.
Changed from f0562e5c17e2ae52b57e231828e38a6fb64d932f to 6c9b8ed0be323a74f28ef5cd7f8cd927f933f27c
Acknowledgement was received that this change introduces only existing code that has been pushed to another public open source repository.

This change contains the following new commits:

Git commit 6c9b8ed0be323a74f28ef5cd7f8cd927f933f27c by Anshil Gandhi on 06/08/2026 at 23:01..
[AMDGPU][GISel] Match constrained shifts across register bank copies

The constrained shift PatFrags (csh_mask_* wrapped by cshl_/csrl_/csra_)
supply GISelPredicateCode and are imported into the GlobalISel match
table, but they never fired for a divergent shift. AMDGPURegBankLegalize
places a cross-bank COPY in two positions inside the shape they match:

 - the mask constant stays in the SGPR bank, so a divergent G_AND reads
   it through a COPY and the frag's imm operand is not a G_CONSTANT;
 - a uniform G_AND feeding a divergent shift is copied to the VGPR bank,
   so the shift's amount operand is not a G_AND.

Either way GIM_CheckOpcode rejects the rule before isUnneededShiftMask
is ever consulted, and the redundant v_and_b32 survives into the output.

Set GIIgnoreCopies so the matcher emits GIM_RecordInsnIgnoreCopies for
those operands. A frag's flags only govern how its own operands are
found, so the first position needs the flag on csh_mask_* while the
second needs it on the node holding the shift; split the masked
alternative of each frag into its own record to carry it there. That
keeps the unmasked alternatives, and the fused patterns built on them,
matching exactly as before. isUnneededShiftMask also has to look through
the copy to read the constant, which getIConstantVRegVal does not do.
SelectionDAG is unaffected, as GISelFlags only feeds the GlobalISel
importer.

This complements the postlegalizer combiner rule from the previous
commit, which runs before the s16 -> s32 widening and bails on vector
types. csh_v4i32 in constrained-shift.ll is a case it cannot reach and
now drops four v_and_b32.

Add inst-select-shift-amount-mask.mir to cover both copy positions and
the rejected cases directly at instruction-select, since the combiner
otherwise removes most masks before selection runs.

Co-authored-by: Cursor <[email protected]>
https://invent.kde.org/qt/clang/llvm-project/-/commit/6c9b8ed0be323a74f28ef5cd7f8cd927f933f27c