[qt/clang/llvm]: Summary of bulk changes made

KDE Git Services - Bulk Change <[email protected]> Fri, 14 Aug 2026 06:12:24 +0000 (UTC)

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Git repository change summary for qt/clang/llvm
Pushed by mirror-service into branch 'upstream/users/rnk/clang-furo-rm-toc'.
Changed from 9492123f7f0301af339b48c5a4aa1ad007caa0ad to b140b122d2594ff0a1ec7f0fbab44de12846a1dc
Acknowledgement was received that this change introduces only existing code that has been pushed to another public open source repository.

This change contains the following new commits:

Git commit 39f708b2c66109308c779bea31cd073a77042234 by GitHub (on behalf of Jianhui Li) on 13/08/2026 at 23:35..
[mlir][mem2reg] Promote whole-buffer memref to a vector SSA value (#211880)

**Problem**
After bufferization, an accumulator that is repeatedly read and written
at a fixed location inside a loop becomes a temporary memref carried
across iterations via transfer_read / transfer_write. These buffers are
pure register-candidates — the memory location is loop-invariant, only
the contents change — but nothing today promotes a whole-buffer
(multi-element) accumulator to a vector SSA value. Upstream mem2reg only
promotes scalar slots.

This PR extends mem2reg to recognize a matching whole-buffer
vector.transfer_read / vector.transfer_write pair as a promotable use,
so the accumulator is promoted to a vector<...> loop iter_arg and the
buffer is eliminated.

**Why not improve the existing tensor/vector hoisting transforms?**

The existing hoisting transforms (hoist_loop_invariant_subsets,
hoist_redundant_vector_transfers) share one method: hoist the read
before the loop, sink the write after it, and thread the value as an
iter_arg. That works only when the accumulator is updated
unconditionally. Once the update is guarded by an scf.if (like in the
case of early exit, masking, prefetch guard), the write lives inside one
branch can't be hoisted. Fixing this requires reaching-definition
analysis over control flow that is exactly what mem2reg already does.

mem2reg complements these transformation: it operates on the lowest
target-independent representation (vector/memref), and is a
well-established, widely-trusted pass rather than a new transform. By
implementing mem2reg's interfaces, this PR introduces a new capability
without much new machinery.

**Minimal example: A GEMM with a dynamic K early-exit**

```
//pseudo code for Linalg/tensor-level representation
D[4][4] = 0 // local accumulator tile, zero-init

for k = 0 to 16 step 4: // walk the K dimension in tiles of 4
if k < dyn_k: // early-exit guard
Atile = A[0:4, k:k+4] // 4x4 slice of A
Btile = B[k:k+4, 0:4] // 4x4 slice of B
D = D + Atile · Btile // accumulate this K-tile into D
// else: skip — D unchanged (and every later k also skips)

C = C + D // add the accumulated tile into C (dest-passing)
return C
```
With the full pipeline (vectorize → LISH →
hoist_redundant_vector_transfers → bufferize → promote-buffers-to-stack
→ buffer-loop-hoisting) the accumulator stays a memref<4x4xf32> alloca,
read/written by the guarded vector.contract.

Adding --mem2reg promotes it to a vector<4x4xf32> iter_arg and
eliminates the buffer.

**What this PR does**

This PR teaches Mem2Reg to promote such a buffer into a single vector
SSA value. memref::AllocaOp::getPromotableSlots now also offers a
vector-typed slot for a static, multi-element memref, and
vector.transfer_read / transfer_write implement
PromotableMemOpInterface as external models, gated by an
isWholeBufferTransfer predicate. Any access that is not a whole-buffer
transfer fails its own canUsesBeRemoved check and aborts promotion.

This PR also implements PromotableAliaserInterface (introduced in
#196924) on memref::SubViewOp. A static, same-rank subview is exposed as
a sub-slice alias of the buffer's slot: a read projects out of the
buffer's vector value with vector.extract_strided_slice, and a write
composes back with vector.insert_strided_slice into the current reaching
definition, so partial and overlapping sub-writes compose in program
order.

It also extends promotion to 1-D scalable buffers: a memref<?x…> sized
vector.vscale * C (accessed by a whole-buffer vector<[C]x…> transfer)
promotes to a scalable vector slot.

**Scope and known limitations**

- Promotes only memref.alloca slots (as scalar mem2reg does) — the
standard non-escaping, statically-shaped local buffer.
- The transfer_read / transfer_write must cover the whole buffer;
partial/strided sub-buffer transfers are not matched.
- vector.load / vector.store are not supported, and memref.reshape,
memref.shape_cast, memref.copy block promotion.
- - No size threshold or opt-out: once --mem2reg runs it promotes every
eligible whole-buffer alloca to a vector regardless of buffer size, so a
large buffer becomes a big-size vector value.

The latter three are limitations of this initial PR and can potentially
be improved down the road

assisted-by-claude

---------

Co-authored-by: Claude Opus 4.8 <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/39f708b2c66109308c779bea31cd073a77042234

Git commit 23ca09c96d24b5cd06f54a3c764e9acede166b44 by GitHub (on behalf of Andy Kaylor) on 13/08/2026 at 23:48..
[CIR] Implement CIRBasicAliasAnalysis::getUnderlyingObject (#215683)

This implements the CIRBasicAliasAnalysis::getUnderlyingObject to follow
casts, pointer strides, array element, and struct member accesses back
to the underlying alloca operation if the operation does not introduce
an offset from the original pointer operand.

This still conservatively returns MayAlias for any comparison involving
a pointer with a non-zero offset from its base alloca address. We could
go further, calculating the offset and determining non-alias or partial
alias from offset pointers, but that is deferred until a future PR.

Assisted-by: Claude / Sonnet-4.6
https://invent.kde.org/qt/clang/llvm/-/commit/23ca09c96d24b5cd06f54a3c764e9acede166b44

Git commit 292670acdb5116b85ad38fe55d585fadd4bd479e by GitHub (on behalf of Andy Kaylor) on 13/08/2026 at 23:50..
[CIR] Handle label address difference (#205437)

This change adds handling for emitting AddrLabelDiff constants. These
constants can be used to initialize static variables within a function
by computing the difference between the addresses of two labels. These
constant values are represented in the AST using the APValue class. The
code generator needs to emit them as initializers for the global
corresponding to the static variable.

This change introduces a new CIR attribute type, BlockAddrDiffAttr to
represent this constant value, deferring the label block address
resolution until we lower the initializer to the LLVM dialect.

Assisted-by: Cursor / claude-opus-4.8
https://invent.kde.org/qt/clang/llvm/-/commit/292670acdb5116b85ad38fe55d585fadd4bd479e

Git commit 14d7ff4e7df451c0c167720853e1a42bfdf5e1bf by GitHub (on behalf of Lang Hames) on 13/08/2026 at 23:56..
[ORC] Align GDB-JIT alloc-action names with the ORC runtime (#216024)

Align LLVM's GDB-JIT registration alloc-action names with the names
added to the ORC runtime in 4a0fdbc25bb, and add a name for the
deregistration action.

Look these names up in the Bootstrap JITDylib rather than the Process
JITDylib. Since the lookup no longer depends on process symbols, drop
the "requires process symbols" preconditions guarding MachO debugger
support in llvm-jitlink and enableDebuggerSupport.
GDBJITDebugInfoRegistrationPlugin::Create also loses its Triple
parameter, which is now unused.

Together this lets GDBJITDebugInfoRegistrationPlugin work against either
the LLVM OrcTargetProcess or ORC runtime implementation of these
actions.
https://invent.kde.org/qt/clang/llvm/-/commit/14d7ff4e7df451c0c167720853e1a42bfdf5e1bf

Git commit a73c52b321e619246b6616850e91889c64205909 by GitHub (on behalf of Andrey Pavlenko) on 14/08/2026 at 00:02..
[mlir][XeGPU] Distribute create_nd_tdesc/load/store with SliceAttr layout (#216104)

## Summary
- `WgToSgCreateNdOp` and `XeGPUWgToSgDistributePass`'s dynamic legality
check only matched `xegpu::LayoutAttr` on a tensor_desc's layout, not
`xegpu::SliceAttr` (also a `DistributeLayoutAttr`).
- A tensor_desc feeding a unit-dim-expanding `vector.shape_cast` carries
a `SliceAttr`, so such `create_nd_tdesc`/`load_nd` ops were left
undistributed while their consumers were already converted to subgroup
shape, causing a `vector.shape_cast` element-count mismatch.
- Match on `DistributeLayoutAttr` instead, consistent with the rest of
the pass (`getSgShapeAndCount`, `genOffsetsList`, etc.).

## Test plan
- [x] Added a regression test to `xegpu-wg-to-sg.mlir`:
`create_nd_tdesc`/`load_nd` with a `SliceAttr` layout feeding
`shape_cast` (expand) → `arith.addf` → `shape_cast` (collapse) →
`store_nd`.
- [x] Verified the new test fails on `main` with the reported error and
passes with this fix.
https://invent.kde.org/qt/clang/llvm/-/commit/a73c52b321e619246b6616850e91889c64205909

Git commit cd3f38b1f4cae586274803bd87a3964d6e69f2c4 by GitHub (on behalf of Jason Molenda) on 14/08/2026 at 00:15..
[lldb][NFC] Remove throwaway variable in conditional expr (#216204)
https://invent.kde.org/qt/clang/llvm/-/commit/cd3f38b1f4cae586274803bd87a3964d6e69f2c4

Git commit 1200fe6f6cece072ba6e7234ad0e29f774b67201 by GitHub (on behalf of Jianhui Li) on 14/08/2026 at 00:28..
[mlir][xegpu] Lower lane_data repack convert_layout to lane_shuffle (#210837)

Extend the SgToLaneConvertLayout pattern to lower a convert_layout that
only repacks lane_data between round-robin and contiguous form (keeping
lane_layout and order unchanged) into xegpu.lane_shuffle. Each lane
keeps the same elements and total bits along the repacked dimension, but
their assignment to lanes changes, so the data is moved across lanes
with a bit-preserving bitcast_shuffle.

assisted-by-claude

---------

Co-authored-by: Claude Opus 4.8 (1M context) <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/1200fe6f6cece072ba6e7234ad0e29f774b67201

Git commit 3d3c04206bca1544dbd3f4e7848e59e64710df7f by GitHub (on behalf of Konstantinos Parasyris) on 14/08/2026 at 00:56..
[CIR][CodeGen] Emit cir.fmuladd for FP-contracted mul+add/sub (#215382)

Ports the FP-contraction fusion from classic CodeGen (`tryEmitFMulAdd` /
`buildFMulAdd`) to CIRGen. Under `-ffp-contract=on / fast`, `a * b + c`
and `a * b - c` fuse into `cir.fmuladd` (with the addend negated for the sub
form) instead of separate `cir.fmul` + `cir.fadd/fsub`.

---------

Co-authored-by: Claude Opus 4.8 (1M context) <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/3d3c04206bca1544dbd3f4e7848e59e64710df7f

Git commit bea2bd1484a3ed036459d20a71007266e88f25b8 by GitHub (on behalf of Alexey Samsonov) on 14/08/2026 at 01:11..
[libc][Semaphore] Fix tests - remove APPEND_LIBC_TEST macro uses. (#216219)

APPEND_LIBC_TEST was removed in abeb492322c12860a4533426208d6d26155cd0bc
, remove it from the newly added semaphore tests as well.
https://invent.kde.org/qt/clang/llvm/-/commit/bea2bd1484a3ed036459d20a71007266e88f25b8

Git commit f33323e92d8f69612929430ebf2963123c7bf8c6 by GitHub (on behalf of Kazu Hirata) on 14/08/2026 at 01:11..
Revert "[Profile] Add a more descriptive message to the bad_header error (#211281)" (#216212)

This reverts commit 806dbe95e7f05b12afd1c7cc579c42e101921199.

insufficient-binary-ids-size.test and truncated-profile.test are
failing on macOS because BSD printf does not support \x hex escapes.

Here are reports of the failures:

https://github.com/llvm/llvm-project/pull/211281#issuecomment-5287429387

https://github.com/llvm/llvm-project/actions/runs/31746112114/job/94601002464?pr=215941
https://invent.kde.org/qt/clang/llvm/-/commit/f33323e92d8f69612929430ebf2963123c7bf8c6

Git commit e76d23748f4c1792137bcbac57572fe928a8ad09 by GitHub (on behalf of Lang Hames) on 14/08/2026 at 01:27..
[ORC] Realign EPCGenericJITLinkMemoryManager Create API (#216216)

Bring EPCGenericJITLinkMemoryManager into alignment with
EPCGenericMemoryAccess and EPCGenericDylibManager: a Bindings
constructor plus static Create methods that build the bindings from the
ProxySpecs using the default controller-interface names.
Create(JITDylib&) resolves the SimpleNativeMemoryMap symbols in the
given JITDylib; Create(ExecutionSession&) uses the bootstrap JITDylib.
Clients targeting a different protocol can construct their own Bindings
directly.

This replaces the previous scheme where Create took a
SimpleExecutorMemoryManagerSymbolNames override.
https://invent.kde.org/qt/clang/llvm/-/commit/e76d23748f4c1792137bcbac57572fe928a8ad09

Git commit 26d1b4f5c0b756f39872d06fb0344cd42029d5c7 by GitHub (on behalf of forking-google-bazel-bot[bot]) on 14/08/2026 at 01:47..
[Bazel] Fixes 39f708b (#216214)

This fixes 39f708b2c66109308c779bea31cd073a77042234 (#211880).

Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=39f708b2c66109308c779bea31cd073a77042234

Co-authored-by: Google Bazel Bot <[email protected]>
https://invent.kde.org/qt/clang/llvm/-/commit/26d1b4f5c0b756f39872d06fb0344cd42029d5c7

Git commit 5e63f2ce42db2c42f1d0012a3b5fa9c6113f750a by GitHub (on behalf of Eric Christopher) on 14/08/2026 at 01:47..
[DebugInfo][NFC] Document debug record salvage (#215907)

Document the order salvageDebugInfoForDbgValues works in: a dbg.assign
address before its variable location, stop once a variable location
can't be salvaged, and kill every supplied record when none of them were
processed.

salvageDebugInfo is documented on both its declaration and its
definition, keep the header copy and update it.

No regressions on check-llvm.
https://invent.kde.org/qt/clang/llvm/-/commit/5e63f2ce42db2c42f1d0012a3b5fa9c6113f750a

Git commit b140b122d2594ff0a1ec7f0fbab44de12846a1dc by Reid Kleckner on 14/08/2026 at 02:05..
Merge main
https://invent.kde.org/qt/clang/llvm/-/commit/b140b122d2594ff0a1ec7f0fbab44de12846a1dc