[stack] Re: Concatenative Hardware Redux (Another 16 Instruction Set)

Hi there,

First, I'm glad to read that kind of post, very suited for FP newbies like me.

    I wonder if the Concatenative group has knowledge of the Forth
effort on the instruction set design front, as published on
ultratechnology.com and discussed in comp.lang.forth . Most notably
the AHA / F21 instruction set and the c18 one. The C18 spec was
adapted for the new SEAForth processors from Intellasys, Mr Moore's
actual(?) employer.

    These imperative-programming guidelines (minimum number of SWAPs
is zero, etc) maybe are not as well suited to one-stack functionnal
programming, I guess you'll be the judges, as I'm barely starting to
grasps basic FP concepts: still wrapping my head around Lisp,
really....

    Nevertheless, I think these FORTH opcodes sets embody a useful
wisdom, if one can see through the veil, to weight the pros and cons
of one's own Most Wonderful Instruction Set, especially if you never
came across them: they're even simpler IMHO (defined in hardware more
clearly? sorry for the poor poo phrasing) than what Christopher
proposed previously, albeit ill-suited for the FP task at hand but
their special instructions sure could be eye-openers.

http://www.ultratechnology.com/f21cpu.html#cpu
http://newsgroups.derkeiler.com/Archive/Comp/comp.lang.forth/2006-06/msg00526.html