Re: Understanding the x18 instruction jump table

--- Jeff Fox <[email protected]> wrote:

> > Article about IntellaSys:
> >
> > Cores That Share Chores
> >
>
http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=12692
> >
> > instruction set list
> >
>
http://www.elecdesign.com/Files/29/12692/Figure_02.jpg
> 
> it takes a very long time for things to go to press
> through
> marketing from engineering so consider them
> preliminary
> 
> next  should say decrement R to -1 then drop R, not
> decrement to 0
> -if   should say jns jump if no sign, ie. msb of T
> is false
> -     should say ones complement of T not A, -1 XOR,
> NOT
> drop;  drop
> 
> It is preliminary, but not quite as preliminary as
> Chuck's
> paper from 2001.

Thanks.  Someone had posted this article on the #c4th
IRC channel.  One of the questions that came up was
the "p" instructions.  (@p+, !p+).  I'm guesing
there's
a "p" register?  The description for !P+ makes sense
(store to address in p; increment) but the @p+ 
description does not (read inline number).  Which
leads me to the next question.  The paper said there
were "32" instructions, but the figure only shows
30.  The figure doesn't show an "N" instruction
to load a litteral (unless @P+ really DOES do that)
and it also doesn't show a way to load the P 
register (no "p!" instruction).  So are those the
other two instructions and they just got accidently
left off of the figure?  But then, the 
SEAforth-24B whitepaper mentioned a "hardware
multiply" and that instruction has to go somewhere.

If I'm going ahead of what you can talk about
right now I understand.

Regards,

John M. Drake

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