Formal Methods in Computer Aided Design 2011 -- First CFP

"David L. Rager" <[email protected]>
Newsgroups gmane.comp.lang.lambda-prolog
Message-ID <[email protected]>
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                             FMCAD 2011                                  
                FORMAL METHODS IN COMPUTER-AIDED DESIGN                  
                        FIRST CALL FOR PAPERS                            
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FIRST CALL FOR PAPERS 
International Conference on Formal Methods in Computer-Aided Design 
http://www.fmcad.org

University of Texas at Austin, Texas, USA 
October 30 - November 2, 2011 


IMPORTANT DATES 

Abstract Submission: May 11 

Paper Submission: May 18 

Author Notification: July 15 

Final Version: August 5 

Conference: October 30 - November 2 


CONFERENCE SCOPE 

FMCAD 2011 is the eleventh in a series of conferences on the theory
and application of formal methods in hardware and system design and
verification. FMCAD provides a leading international forum to
researchers and practitioners in academia and industry for presenting
and discussing novel methods, technologies, theoretical results, and
tools for formal reasoning about computing systems, as well as open
challenges therein.

This year, FMCAD is privileged to have J Moore, a winner of the ACM
System Award (2005), member of National Academy of Engineering, and
ACM Fellow, as an invited speaker.

So far Aarti Gupta, a senior researcher at NEC, Ivan Sutherland, a
Turing Award winner (1988), and John Hughes, Professor at Chalmers
University of Technology and CEO of QuviQ, have accepted invitations
to be tutorial speakers.


TOPICS OF INTEREST 

Advances in model checking, theorem proving, equivalence checking,
abstraction and reduction techniques, compositional methods, automatic
decision procedures at the bit and word-level, probabilistic methods,
and combinations of deductive methods and decision procedures.

Topics related to the application of formal and semi-formal methods to
functional and non-functional specification and validation of hardware
and software. This includes timing and power modeling, and
verification of computing systems on all levels of abstraction.

System-level design and verification, especially for embedded systems,
HW/SW co-design and verification, and transaction-level verification.

Modeling and specification languages, formal semantics of known
languages or their subsets, model-based design, design derivation and
transformation, and correct-by-construction methods.

Experience with the application of formal and semi-formal methods to
industrial-scale designs. Tools that represent FV enablement, new
features, or a substantial improvement in the automation of FV
methods.

Application of formal methods in new areas. 


SUBMISSIONS 

Submissions must be made electronically in PDF format via EasyChair.
More details will be provided on the FMCAD web site. The proceedings
will be available online in the ACM Digital Library, at IEEE Xplore,
and as a free download from the FMCAD web site.  Two categories of
papers can be submitted: regular papers (8 pages), containing original
research that has not been previously published, nor concurrently
submitted for publication; and short papers (4 pages), containing
emerging results or original ideas that can be described succinctly.

Regular and short papers must use the IEEE Transactions format on
letter-size paper with a 10-point font size, see
http://www.ieee.org/portal/pages/pubs/transactions/stylesheets.html.
We recommend that self-citations be written in the third
person. Submissions must contain original research that has not been
previously published, nor concurrently submitted for publication. Any
partial overlap with any published or concurrently submitted paper
must be clearly indicated.  If experimental results are reported,
authors are strongly encouraged to provide adequate access to their
data so that results can be independently verified.

A small number of accepted papers will be considered for a
distinguished paper award.


ASSOCIATED WORKSHOPS AND COMPETITION

The ACL2 workshop, the Design and Implementation of Formal Tools and
Systems (DIFTS) workshop, and the Hardware Model Checking Competition
(HWMCC) will be co-located with FMCAD.


GENERAL CHAIRS 

Per Bjesse, Synopsys Inc., Hillsboro, USA 
Anna Slobodova, Centaur Technology, Austin, USA 


LOCAL ARRANGEMENTS 

David Rager, University of Texas at Austin, USA 


STEERING COMMITTEE 

Jason Baumgartner, IBM, USA 
Aarti Gupta, NEC Labs America, USA 
Warren Hunt, University of Texas at Austin, USA 
Panagiotis Manolios, Northeastern University, USA 
Mary Sheeran, Chalmers University of Technology, Sweden 


PROGRAM COMMITTEE 

Barbara Jobstmann (TUTORIALS CHAIR), VERIMAG, France 
Viktor Kuncak (PUBLICATION CHAIR), EPFL, Switzerland 
Nina Amla, NSF, USA 
Jason Baumgartner, IBM, USA 
Armin Biere, Johannes Kepler University, Austria 
Roderick Bloem, Graz University of Technology, Austria 
Doron Bustan, University of Warwick, UK 
Gianpiero Cabodi, Politecnico di Torino, Italy 
Alessandro Cimatti, FBK-IRST, Italy 
Koen Claessen, Chalmers University of Technology, Sweden 
Rolf Drechsler, University of Bremen, Germany 
Bruno Duterte, SRI, USA 
Ganesh Gopalakrishnan, University of Utah, USA 
Aarti Gupta, NEC Labs America, USA 
Alan Hu, University of British Columbia, Canada 
Rick Huang, National Taiwan University, Taiwan 
Gerwin Klein, NICTA, Sydney, Australia 
Daniel Kroening, University of Oxford, UK 
Thomas Kropf, Robert Bosch GmbH, Germany 
Oded Maler, VERIMAG, France 
Panagiotis Manolios, Northeastern University, USA 
Ken McMillan, Microsoft Research, Seattle, USA 
Tom Melham, University of Oxford, UK 
Lee Pike, Galois, USA 
Kavita Ravi, Cadence, USA 
Sandip Ray, University of Texas at Austin, USA 
Julien Schmalz, Open University of the Netherlands, The Netherlands 
Natasha Sharygina, University of Lugano, Switzerland 
Satnam Singh, Microsoft Research, Cambridge, UK 
Sofiene Tahar, Concordia University, Montreal, Canada 
Murali Talupur, Intel, Portland, Oregon, USA 
Helmut Veith, Technical University of Darmstadt, Germany 
Karen Yorav, IBM, Israel
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