Postdoc/PhD Opportunity at the University of California, Irvine

Ayoub Nouri <[email protected]> Wed, 25 Oct 2017 11:47:11 +0200
Newsgroups gmane.comp.science.types.announce,gmane.science.mathematics.categories,gmane.comp.lang.haskell.general,gmane.comp.lang.lambda-prolog
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[ The Types Forum (announcements only),
     http://lists.seas.upenn.edu/mailman/listinfo/types-announce ]


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[Apologies for cross-posting]

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Postdoc/PhD Opportunity at the University of California, Irvine


Project Title: Conquering MPSoC Complexity with Principles of a 
Self-Aware Information Processing Factory

Host: Univ. of California, Irvine, Center for Embedded & Cyber-physical 
Systems, Irvine, CA, USA.

     Supervisor/Contact Person: Prof. Fadi Kurdahi ([email protected]) 
<mailto:[email protected]%29>

     Co-supervisor: Prof. Nikil Dutt ([email protected]) 
<mailto:[email protected]%29>.


Requirements:

     Postdoc: PhD degree in CS, Computer Engineering or EE from a top 
University.

     PhD: Master’s in Computer Science, Computer Engineering or 
equivalent from a top University


Objectives:

     Develop and evaluate hardware-assisted runtime verification models, 
architectures and tools.

     Develop evaluate machine learning-based specification mining 
methods and tools.


Expected Skills:

     Familiarity with hardware-assisted runtime verification formalism, 
tools and methods

     Familiarity with machine-learning algorithms

     Familiarity with specification mining methods and applications.

     Experience with FPGA tools

     Experience with multiprocessor simulators such as GEM5.


Planned visits and collaboration:

     TU Munich (Professor Andreas Herkersdorf)

     TU Branschweig (Professor Rolf Ernst)


Timeline:

    Ideally, candidates would be able to start in Winter or Spring 2018 
for a period of 1 year with possibility of extension up to 3 years total.


To Inquire: Please send a CV to Fadi Kurdahi ([email protected]) 
<mailto:[email protected]%29>.


Relevant publications:

Nikil Dutt, Fadi J. Kurdahi, Rolf Ernst, and Andreas Herkersdorf. 2016. 
Conquering MPSoC complexity with principles of a self-aware information 
processing factory. In /Proceedings of the Eleventh IEEE/ACM/IFIP 
International Conference on Hardware/Software Codesign and System 
Synthesis/ (CODES '16). ACM, New York, NY, USA, Article 37, 4 pages. 
DOI: https://doi.org/10.1145/2968456.2973275].

Ahmed Nassar, Fadi J. Kurdahi, and Wael Elsharkasy. 2015. NUVA: 
architectural support for runtime verification of parametric 
specifications over multicores. In /Proceedings of the 2015 
International Conference on Compilers, Architecture and Synthesis for 
Embedded Systems/ (CASES '15). IEEE Press, Piscataway, NJ, USA, 137-146.

A. Nassar, F. J. Kurdahi and S. R. Zantout, "Topaz: Mining high-level 
safety properties from logic simulation traces," /2016 Design, 
Automation & Test in Europe Conference & Exhibition (DATE)/, Dresden, 
2016, pp. 1473-1476

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    <p class="MsoNormal"><span style="font-size:11.0pt">[Apologies for
        cross-posting]</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">-------------------------------------------------------------------------------------------------<br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Postdoc/PhD
        Opportunity at the University of California, Irvine</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Project Title:
        Conquering MPSoC Complexity with Principles of a Self-Aware
        Information Processing Factory</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Host: Univ. of
        California, Irvine, Center for Embedded &amp; Cyber-physical
        Systems, Irvine, CA, USA.</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Supervisor/Contact
        Person: Prof. Fadi Kurdahi (<a href="mailto:[email protected]%29">[email protected])</a></span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Co-supervisor:
        Prof. Nikil Dutt (<a href="mailto:[email protected]%29">[email protected])</a>.
        <br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Requirements:</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Postdoc: PhD
        degree in CS, Computer Engineering or EE from a top University. </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    PhD:
        Master’s in Computer Science, Computer Engineering or equivalent
        from a top University</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Objectives:</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Develop and
        evaluate hardware-assisted runtime verification models,
        architectures and tools.</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Develop
        evaluate machine learning-based specification mining methods and
        tools.</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Expected Skills:</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Familiarity
        with hardware-assisted runtime verification formalism, tools and
        methods</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Familiarity
        with machine-learning algorithms  </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Familiarity
        with specification mining methods and applications. </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Experience
        with FPGA tools  </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    Experience
        with multiprocessor simulators such as GEM5. <br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Planned visits
        and collaboration:</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    TU Munich
        (Professor Andreas Herkersdorf)</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">    TU
        Branschweig (Professor Rolf Ernst)</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Timeline: <br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">   Ideally,
        candidates would be able to start in Winter or Spring 2018 for a
        period of 1 year with possibility of extension up to 3 years
        total.</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">To Inquire:
        Please send a CV to Fadi Kurdahi (<a
          href="mailto:[email protected]%29">[email protected])</a>. <br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt"><br>
      </span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Relevant
        publications:</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Nikil Dutt, Fadi
        J. Kurdahi, Rolf Ernst, and Andreas Herkersdorf. 2016.
        Conquering MPSoC complexity with principles of a self-aware
        information processing factory. In <i>Proceedings of the
          Eleventh IEEE/ACM/IFIP International Conference on
          Hardware/Software Codesign and System Synthesis</i> (CODES
        '16). ACM, New York, NY, USA, Article 37, 4 pages. DOI: <a
          href="https://doi.org/10.1145/2968456.2973275">https://doi.org/10.1145/2968456.2973275</a>].</span></p>
    <p class="MsoNormal"><span style="font-size:11.0pt">Ahmed Nassar,
        Fadi J. Kurdahi, and Wael Elsharkasy. 2015. NUVA: architectural
        support for runtime verification of parametric specifications
        over multicores. In <i>Proceedings of the 2015 International
          Conference on Compilers, Architecture and Synthesis for
          Embedded Systems</i> (CASES '15). IEEE Press, Piscataway, NJ,
        USA, 137-146.</span></p>
    <span style="font-size:11.0pt">A. Nassar, F. J. Kurdahi and S. R.
      Zantout, "Topaz: Mining high-level safety properties from logic
      simulation traces," <i>2016 Design, Automation &amp; Test in
        Europe Conference &amp; Exhibition (DATE)</i>, Dresden, 2016,
      pp. 1473-1476</span>
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