[MLton] MLton on the bare metal or RTOS

I'd like to use MLton to compile code for an ARM Cortex-M3 SOC. I'd like to
develop in ML, rather than in C. I would use an existing RTOS and drivers
to avoid real time requirements, so I could use a GC. The GC, and threads
are the only parts of the runtime I would definitely need.

I think there is probably only one crucial question: does the GC need an
MMU? If its just case of needing to know the physical address of the heap
and stack in advance that can probably be calculated. Also, I can protect
memory regions to achieve a write barrier, if that's required.

Cheers
David

------------------------------------------------------------------------------
Meet PCI DSS 3.0 Compliance Requirements with EventLog Analyzer
Achieve PCI DSS 3.0 Compliant Status with Out-of-the-box PCI DSS Reports
Are you Audit-Ready for PCI DSS 3.0 Compliance? Download White paper
Comply to PCI DSS 3.0 Requirement 10 and 11.5 with EventLog Analyzer
http://pubads.g.doubleclick.net/gampad/clk?id=154622311&iu=/4140/ostg.clktrk

_______________________________________________
MLton-devel mailing list
[email protected]; [email protected]
https://lists.sourceforge.net/lists/listinfo/mlton-devel