CVS: sml-dist/src/compiler/Elaborator/modules sigmatch.sml, 1.6.8.9, 1.6.8.10

George Kuan <[email protected]> Tue, 18 Jul 2006 07:15:39 -0700
Newsgroups gmane.comp.lang.sml.smlnj.commits
Message-ID <[email protected]>
Update of /cvsroot/smlnj/sml-dist/src/compiler/Elaborator/modules
In directory sc8-pr-cvs8.sourceforge.net:/tmp/cvs-serv16564/src/compiler/Elaborator/modules

Modified Files:
      Tag: primop-branch-2
	sigmatch.sml 
Log Message:
debug printout for getStrElem/getFctElem (slot selection on empty strPrimInfo) bug

Index: sigmatch.sml
===================================================================
RCS file: /cvsroot/smlnj/sml-dist/src/compiler/Elaborator/modules/sigmatch.sml,v
retrieving revision 1.6.8.9
retrieving revision 1.6.8.10
diff -C2 -d -r1.6.8.9 -r1.6.8.10
*** sigmatch.sml	12 Jul 2006 15:43:13 -0000	1.6.8.9
--- sigmatch.sml	18 Jul 2006 14:15:36 -0000	1.6.8.10
***************
*** 1239,1243 ****
                (case (EE.look(resEntEnv, ev), EE.look(srcEntEnv, ev))  
                   of (M.STRent resStrRlzn, M.STRent srcStrRlzn) =>
! 		     let val srcStr = M.STR{sign=thisSpecsig, rlzn=srcStrRlzn,
  					    access=DA.selAcc(rootAcc,s),
  					    prim=PrimOpId.selStrPrimId(rootInfo,s)}
--- 1239,1244 ----
                (case (EE.look(resEntEnv, ev), EE.look(srcEntEnv, ev))  
                   of (M.STRent resStrRlzn, M.STRent srcStrRlzn) =>
! 		     let val _ = print "packElems\n"
! 			 val srcStr = M.STR{sign=thisSpecsig, rlzn=srcStrRlzn,
  					    access=DA.selAcc(rootAcc,s),
  					    prim=PrimOpId.selStrPrimId(rootInfo,s)}
***************
*** 1267,1271 ****
                (case (EE.look(resEntEnv, ev), EE.look(srcEntEnv, ev))
  		 of (M.FCTent resFctRlzn, M.FCTent srcFctRlzn) =>
! 		     let val srcFct =
  			     M.FCT {sign=thisSpecsig, rlzn=srcFctRlzn,
  				    access=DA.selAcc(rootAcc,s),
--- 1268,1273 ----
                (case (EE.look(resEntEnv, ev), EE.look(srcEntEnv, ev))
  		 of (M.FCTent resFctRlzn, M.FCTent srcFctRlzn) =>
! 		     let val _ = print "packElems FCTspec\n"
! 			 val srcFct =
  			     M.FCT {sign=thisSpecsig, rlzn=srcFctRlzn,
  				    access=DA.selAcc(rootAcc,s),


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