CVS: sml-dist/src/MLRISC/amd64/instructions amd64comp-instr-ext.sml, 1.1, 1.2

Update of /cvsroot/smlnj/sml-dist/src/MLRISC/amd64/instructions
In directory sc8-pr-cvs8.sourceforge.net:/tmp/cvs-serv30638/src/MLRISC/amd64/instructions

Modified Files:
	amd64comp-instr-ext.sml 
Log Message:
merged amd64 code from Mike Rainey

Index: amd64comp-instr-ext.sml
===================================================================
RCS file: /cvsroot/smlnj/sml-dist/src/MLRISC/amd64/instructions/amd64comp-instr-ext.sml,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** amd64comp-instr-ext.sml	5 Oct 2006 15:09:16 -0000	1.1
--- amd64comp-instr-ext.sml	5 Oct 2006 16:26:29 -0000	1.2
***************
*** 47,52 ****
      (I.instruction, I.C.cellset, I.operand, I.addressing_mode, CFG.cfg) TS.reducer
  
!   val esp = C.esp
!   val espOpnd = I.Direct(esp)
  
    fun error msg = MLRiscErrorMsg.error("AMD64CompInstrExt", msg)
--- 47,52 ----
      (I.instruction, I.C.cellset, I.operand, I.addressing_mode, CFG.cfg) TS.reducer
  
!   val esp = C.rsp
!   val espOpnd = I.Direct(64,esp)
  
    fun error msg = MLRiscErrorMsg.error("AMD64CompInstrExt", msg)
***************
*** 79,83 ****
         (* src must in a register *)
         emit(I.cmpxchg{lock=true,sz=I.I32, 
!                       src=I.Direct(reduceOperand(operand src)), 
                        dst=operand dst},an)
    end
--- 79,83 ----
         (* src must in a register *)
         emit(I.cmpxchg{lock=true,sz=I.I32, 
!                       src=I.Direct(64,reduceOperand(operand src)), 
                        dst=operand dst},an)
    end


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