[PATCH] x86: Complete MSRLIST support
"H.J. Lu" <[email protected]>
| Newsgroups | gmane.comp.lib.glibc.alpha |
|---|---|
| Message-ID | <CAMe9rOpacezDrbQCZRvp1rst-sqBA5Jc8oiuHK-kkmzFGax_vw@mail.gmail.com> |
Define bit_cpu_MSRLIST, index_cpu_MSRLIST and reg_MSRLIST. -- H.J.
0001-x86-Complete-MSRLIST-support.patch
(text/x-patch, 1.3 KB)
From ad62b0e7e0fe5d1819bc2073149b623f0e3ecc43 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" <[email protected]> Date: Mon, 24 Aug 2026 05:55:32 +0800 Subject: [PATCH] x86: Complete MSRLIST support Define bit_cpu_MSRLIST, index_cpu_MSRLIST and reg_MSRLIST. Signed-off-by: H.J. Lu <[email protected]> --- sysdeps/x86/include/cpu-features.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 8b35fc8196..c1ef3911ab 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -313,6 +313,7 @@ enum #define bit_cpu_HRESET (1u << 22) #define bit_cpu_AVX_IFMA (1u << 23) #define bit_cpu_LAM (1u << 26) +#define bit_cpu_MSRLIST (1u << 27) /* EDX. */ #define bit_cpu_AVX_VNNI_INT8 (1u << 4) @@ -567,6 +568,9 @@ enum #define index_cpu_HRESET CPUID_INDEX_7_ECX_1 #define index_cpu_AVX_IFMA CPUID_INDEX_7_ECX_1 #define index_cpu_LAM CPUID_INDEX_7_ECX_1 +#define index_cpu_MSRLIST CPUID_INDEX_7_ECX_1 + +/* EDX. */ #define index_cpu_AVX_VNNI_INT8 CPUID_INDEX_7_ECX_1 #define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1 #define index_cpu_AMX_COMPLEX CPUID_INDEX_7_ECX_1 @@ -819,6 +823,7 @@ enum #define reg_HRESET eax #define reg_AVX_IFMA eax #define reg_LAM eax +#define reg_MSRLIST eax /* EDX. */ #define reg_AVX_VNNI_INT8 edx -- 2.55.0