Re: Cheap pinpad smart card reader with "PIN firewall"
Ludovic Rousseau <[email protected]>
| Newsgroups | gmane.comp.encryption.opensc.devel,gmane.comp.lib.muscle |
|---|---|
| Message-ID | <CAGstE8DHNqonWofVbr3oshvN6V5iWaiQ+Odsw0S0r4Gyeu1-4g@mail.gmail.com> |
2013/10/19 Martin Paljak <[email protected]>: > On Wed, Oct 16, 2013 at 7:21 PM, Ludovic Rousseau > <[email protected]> wrote: >> To check the features of a (recent) Gemalto reader you can use my >> FEATURE_CCID_ESC_COMMAND_Gemalto_features.py [1] Python script from >> the pcsc-lite repository. >> >> Martin, can you run the script with CT710 connected and publish the results? > > The output of the script is attached. Thanks. Added to my collection. > It is strange that they have reduced the maximum PIN length number :( And they have fixed the FirewalledCommand_SW1/SW2, and added a USB Cserial number. Compared to the CT710 I have access to: --- Gemalto_Ezio_Shield_PinPad_features.txt 2013-10-19 18:37:10.000000000 +0200 +++ /Users/rousseau/Downloads/Martin.txt 2013-10-19 19:48:56.000000000 +0200 @@ -1,7 +1,11 @@ -Reader: Gemalto Ezio Shield 00 00 +Reader: Gemalto Ezio Shield (S1370135513869) 00 00 IdVendor: 0x08E6 IdProduct: 0x34C2 -[2, 17, 0, 2, 127, 0, 0, 0, 6, 0, 0, 0, 1, 4, 16, 1, 255, 255, 0, 0, 0] +[2, 17, 0, 2, 127, 0, 0, 0, 6, 0, 0, 0, 1, 4, 12, 1, 100, 4, 0, 0, 0] LogicalLCDLineNumber (Logical number of LCD lines): 2 LogicalLCDRowNumber (Logical number of characters per LCD line): 17 LcdInfo: 0 @@ -33,7 +37,7 @@ bPPDUSupportOverEscape: False VersionNumber: 1 MinimumPINSize: 4 -MaximumPINSize: 16 +MaximumPINSize: 12 Firewall: True -FirewalledCommand_SW1: 0xFF -FirewalledCommand_SW2: 0xFF +FirewalledCommand_SW1: 0x64 +FirewalledCommand_SW2: 0x04 -- Dr. Ludovic Rousseau ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60135031&iu=/4140/ostg.clktrk